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1. general description the lpc11cx2/cx4 are an arm cortex-m0 bas ed, low-cost 32-bit mcu family, designed for 8/16-bit microcontroller applications, offering performance, low power, simple instruction set and memory addressing together with reduced code size compared to existing 8/16-bit architectures. the lpc11cx2/cx4 operate at cpu frequencies of up to 50 mhz. the peripheral complement of the lpc11cx2 /cx4 includes 16/32 kb of flash memory, 8 kb of data memory, one c_can controller, one fast-mode plus i 2 c-bus interface, one rs-485/eia-485 uart, two spi interfaces with ssp featur es, four gener al purpose counter/timers, a 10-bit adc, and up to 40 general purpose i/o pins. on-chip c_can drivers and flash in-system programming tools via c_can are included. in addition, the lpc11c22 and lpc11c24 pa rts include an on-chip, high-speed can transceiver. 2. features and benefits ? system: ? arm cortex-m0 processor, running at frequencies of up to 50 mhz. ? arm cortex-m0 built-in nested vectored interrupt controller (nvic). ? serial wire debug. ? system tick timer. ? memory: ? 32 kb (lpc11cx4) or 16 kb (lpc11cx2) on-chip flash program memory. ? 8 kb sram data memory. ? in-system programming (isp) and in-application programming (iap) via on-chip bootloader software. ? flash isp commands can be issued via uart or c_can. ? digital peripherals: ? general purpose i/o (gpio) pins with c onfigurable pull-up/pu ll-down resistors. ? 40 gpio pins on the lpc11c12/c14 parts; 36 gpio pins on the lpc11c22/c24 parts. ? gpio pins can be used as edge and level sensitive interrupt sources. ? high-current output driver (20 ma) on one pin. ? high-current sink drivers (20 ma) on two i 2 c-bus pins in fast-mode plus. ? four general purpose counter/timers with a total of four capture inputs and 13 (lpc11c12/c14) or 12 (lpc 11c22/c24) match outputs. lpc11cx2/cx4 32-bit arm cortex-m0 microcontrolle r; 16/32 kb flash, 8 kb sram; c_can rev. 3.1 ? 15 may 2013 product data sheet
lpc11cx2_cx4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3.1 ? 15 may 2013 2 of 62 nxp semiconductors lpc11cx2/cx4 32-bit arm cortex-m0 microcontroller ? programmable watchdog timer (wdt). ? analog peripherals: ? 10-bit adc with input multiplexing among 8 pins. ? serial interfaces: ? uart with fractional baud rate generation, internal fifo, and rs-485 support. ? two spi controllers with ssp features and with fifo and multi-protocol capabilities. ? i 2 c-bus interface supporting full i 2 c-bus specification and fast-mode plus with a data rate of 1 mbit/s with multiple address reco gnition and monitor mode. ? c_can controller. on-chip c_ca n and canopen drivers included. ? on-chip, high-speed can transceiver (parts lpc11c22/c24 only). ? clock generation: ? 12 mhz internal rc oscillator trimmed to 1 % accuracy that can optionally be used as a system clock. ? crystal oscillator with an operating range of 1 mhz to 25 mhz. ? programmable watchdog oscillator with a frequency range of 7.8 khz to 1.8 mhz. ? pll allows cpu operation up to the maximum cpu rate without the need for a high-frequency crystal. may be run from th e system oscillator or the internal rc oscillator. ? clock output function with divider that ca n reflect the system oscillator, irc, cpu clock, or the watchdog clock. ? power control: ? integrated pmu (power management unit) to minimize power consumption during sleep, deep-sleep, and deep power-down modes. ? three reduced power modes: sleep, deep-sleep, and deep power-down. ? processor wake-up from deep-sleep mode via a dedicated start logic using 13 of the gpio pins. ? power-on reset (por). ? brownout detect with four separate thre sholds for interrup t and forced reset. ? unique device serial number for identification. ? single 3.3 v power supply (1.8 v to 3.6 v). ? available as 48-pin lqfp package. 3. applications ? emetering ? industrial and sensor based networks ? elevator systems ? white goods
lpc11cx2_cx4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3.1 ? 15 may 2013 3 of 62 nxp semiconductors lpc11cx2/cx4 32-bit arm cortex-m0 microcontroller 4. ordering information 4.1 ordering options table 1. ordering information type number package name description version LPC11C12FBD48/301 lqfp48 lqfp48: plastic low pr ofile quad flat package; 48 leads; body 7 ? 7 ? 1.4 mm sot313-2 lpc11c14fbd48/301 lqfp48 lqfp48: plastic low pr ofile quad flat package; 48 leads; body 7 ? 7 ? 1.4 mm sot313-2 lpc11c22fbd48/301 lqfp48 lqfp48: plastic low pr ofile quad flat package; 48 leads; body 7 ? 7 ? 1.4 mm sot313-2 lpc11c24fbd48/301 lqfp48 lqfp48: plastic low pr ofile quad flat package; 48 leads; body 7 ? 7 ? 1.4 mm sot313-2 table 2. ordering options type number flash total sram uart rs-485 i 2 c/ fast+ spi c_can c_can with on-chip can transceiver gpio pins adc channels package LPC11C12FBD48/301 16 kb 8 kb 1 1 2 1 no 40 8 lqfp48 lpc11c14fbd48/301 32 kb 8 kb 1 1 2 1 no 40 8 lqfp48 lpc11c22fbd48/301 16 kb 8 kb 1 1 2 1 yes 36 8 lqfp48 lpc11c24fbd48/301 32 kb 8 kb 1 1 2 1 yes 36 8 lqfp48
lpc11cx2_cx4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3.1 ? 15 may 2013 4 of 62 nxp semiconductors lpc11cx2/cx4 32-bit arm cortex-m0 microcontroller 5. block diagram (1) ct16b1_mat0 not available on parts lpc11c22/c24. fig 1. lpc11cx2/cx4 block diagram sram 8 kb arm cortex-m0 test/debug interface flash 16/32 kb high-speed gpio ahb to apb bridge clock generation, power control, system functions xtalin xtalout reset clocks and controls swd lpc11cx2/cx4 002aaf265 slave slave slave slave rom slave ahb-lite bus gpio ports pio0/1/2/3 clkout irc por spi0 10-bit adc uart 32-bit counter/timer 0 i 2 c-bus wdt ioconfig ct32b0_mat[3:0] ad[7:0] ct32b0_cap0 sda scl rxd txd dtr, dsr, cts, dcd, ri, rts system control pmu 32-bit counter/timer 1 ct32b1_mat[3:0] ct32b1_cap0 16-bit counter/timer 1 ct16b1_mat[1:0] (1) ct16b1_cap0 c_can (lpc11c12/c14) can_txd can_rxd c_can/ on-chip transceiver (lpc11c22/c24) canl, canh stb v cc , vdd_can 16-bit counter/timer 0 ct16b0_mat[2:0] ct16b0_cap0 sck0, ssel0 miso0, mosi0 sck1, ssel1 miso1, mosi1 spi1 system bus
lpc11cx2_cx4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3.1 ? 15 may 2013 5 of 62 nxp semiconductors lpc11cx2/cx4 32-bit arm cortex-m0 microcontroller 6. pinning information 6.1 pinning fig 2. pin configuration (lpc11c12/c14) LPC11C12FBD48/301 lpc11c14fbd48/301 pio2_6 pio3_0/dtr pio2_0/dtr/ssel1 r/pio1_2/ad3/ct32b1_mat1 reset/pio0_0 r/pio1_1/ad2/ct32b1_mat0 pio0_1/clkout/ct32b0_mat2 r/pio1_0/ad1/ct32b1_cap0 v ss r/pio0_11/ad0/ct32b0_mat3 xtalin pio2_11/sck0 xtalout pio1_10/ad6/ct16b1_mat1 v dd swclk/pio0_10/sck0/ct16b0_mat2 pio1_8/ct16b1_cap0 pio0_9/mosi0/ct16b0_mat1 pio0_2/ssel0/ct16b0_cap0 pio0_8/miso0/ct16b0_mat0 pio2_7 pio2_2/dcd/miso1 pio2_8 pio2_10 pio2_1/dsr/sck1 pio3_3/ri pio0_3 pio1_7/txd/ct32b0_mat1 pio0_4/scl pio1_6/rxd/ct32b0_mat0 pio0_5/sda pio1_5/rts/ct32b0_cap0 pio1_9/ct16b1_mat0 v dd pio2_4 pio3_2/dcd can_rxd pio1_11/ad7 can_txd v ss pio2_5 pio1_4/ad5/ct32b1_mat3/wakeup pio0_6/sck0 swdio/pio1_3/ad4/ct32b1_mat2 pio0_7/cts pio2_9 pio2_3/ri/mosi1 pio3_1/dsr 002aaf266 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 48 47 46 45 44 43 42 41 40 39 38 37 24
lpc11cx2_cx4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3.1 ? 15 may 2013 6 of 62 nxp semiconductors lpc11cx2/cx4 32-bit arm cortex-m0 microcontroller fig 3. pin configuration (lpc11c22/c24) lpc11c22fbd48/301 lpc11c24fbd48/301 pio2_6 pio3_0/dtr pio2_0/dtr/ssel1 r/pio1_2/ad3/ct32b1_mat1 reset/pio0_0 r/pio1_1/ad2/ct32b1_mat0 pio0_1/clkout/ct32b0_mat2 r/pio1_0/ad1/ct32b1_cap0 v ss r/pio0_11/ad0/ct32b0_mat3 xtalin pio2_11/sck0 xtalout pio1_10/ad6/ct16b1_mat1 v dd swclk/pio0_10/sck0/ct16b0_mat2 pio1_8/ct16b1_cap0 pio0_9/mosi0/ct16b0_mat1 pio0_2/ssel0/ct16b0_cap0 pio0_8/miso0/ct16b0_mat0 pio2_7 pio2_2/dcd/miso1 pio2_8 pio2_10 pio2_1/dsr/sck1 pio3_3/ri pio0_3 pio1_7/txd/ct32b0_mat1 pio0_4/scl pio1_6/rxd/ct32b0_mat0 pio0_5/sda pio1_5/rts/ct32b0_cap0 vdd_can v dd canl pio3_2/dcd canh pio1_11/ad7 v cc v ss gnd pio1_4/ad5/ct32b1_mat3/wakeup stb swdio/pio1_3/ad4/ct32b1_mat2 pio0_6/sck0 pio0_7/cts pio2_3/ri/mosi1 pio3_1/dsr 002aaf909 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 48 47 46 45 44 43 42 41 40 39 38 37 24
lpc11cx2_cx4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3.1 ? 15 may 2013 7 of 62 nxp semiconductors lpc11cx2/cx4 32-bit arm cortex-m0 microcontroller 6.2 pin description table 3. lpc11c12/c14 pin description table symbol pin start logic inputs type reset state [1] description pio0_0 to pio0_11 port 0 ? port 0 is a 12-bit i/o port with individual direction and function controls for each bit. the operation of port 0 pins depends on the function selected through the ioconfig register block. reset /pio0_0 3 [2] yes i i; pu reset ? external reset input with 20 ns glitch filter. a low-going pulse as short as 50 ns on this pin resets the device, causing i/o ports and peripherals to take on their default states, and processor execution to begin at address 0. i/o - pio0_0 ? general purpose digital input/ output pin with 10 ns glitch filter. pio0_1/clkout/ ct32b0_mat2 4 [3] yes i/o i; pu pio0_1 ? general purpose digital input/ output pin. a low level on this pin during reset starts the flash isp command handler via uart (if pio0_3 is high) or via c_can (if pio0_3 is low). o- clkout ? clockout pin. o- ct32b0_mat2 ? match output 2 for 32-bit timer 0. pio0_2/ssel0/ ct16b0_cap0 10 [3] yes i/o i; pu pio0_2 ? general purpose digital input/output pin. i/o - ssel0 ? slave select for spi0. i- ct16b0_cap0 ? capture input 0 for 16-bit timer 0. pio0_3 14 [3] yes i/o i; pu pio0_3 ? general purpose digital input/output pin. this pin is monitored during reset: together with a low level on pin pio0_1, a low level starts the flash isp command handler via c_can and a high level starts the flash isp command handler via uart. pio0_4/scl 15 [4] yes i/o i; ia pio0_4 ? general purpose digital input/output pin (open-drain). i/o - scl ? i 2 c-bus, open-drain clock input/output. high-current sink only if i 2 c fast-mode plus is selected in the i/o configuration register. pio0_5/sda 16 [4] yes i/o i; ia pio0_5 ? general purpose digital input/output pin (open-drain). i/o - sda ? i 2 c-bus, open-drain data input/ou tput. high-current sink only if i 2 c fast-mode plus is selected in the i/o configuration register. pio0_6/sck0 22 [3] yes i/o i; pu pio0_6 ? general purpose digital input/output pin. i/o - sck0 ? serial clock for spi0. pio0_7/cts 23 [3] yes i/o i; pu pio0_7 ? general purpose digital input/output pin (high-current output driver). i- cts ? clear to send input for uart. pio0_8/miso0/ ct16b0_mat0 27 [3] yes i/o i; pu pio0_8 ? general purpose digital input/output pin. i/o - miso0 ? master in slave out for spi0. o- ct16b0_mat0 ? match output 0 for 16-bit timer 0. pio0_9/mosi0/ ct16b0_mat1 28 [3] yes i/o i; pu pio0_9 ? general purpose digital input/output pin. i/o - mosi0 ? master out slave in for spi0. o- ct16b0_mat1 ? match output 1 for 16-bit timer 0. swclk/pio0_10/ sck0/ ct16b0_mat2 29 [3] yes i i; pu swclk ? serial wire clock. i/o - pio0_10 ? general purpose digi tal input/output pin. i/o - sck0 ? serial clock for spi0. o- ct16b0_mat2 ? match output 2 for 16-bit timer 0.
lpc11cx2_cx4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3.1 ? 15 may 2013 8 of 62 nxp semiconductors lpc11cx2/cx4 32-bit arm cortex-m0 microcontroller r/pio0_11/ ad0/ ct32b0_mat3 32 [5] yes - i; pu r ? reserved. configure for an alternate function in the ioconfig block. i/o - pio0_11 ? general purpose digital input/output pin. i- ad0 ? a/d converter, input 0. o- ct32b0_mat3 ? match output 3 for 32-bit timer 0. pio1_0 to pio1_11 port 1 ? port 1 is a 12-bit i/o port with individual direction and function controls for each bit. the operation of port 1 pins depends on the function selected through the ioconfig register block. r/pio1_0/ad1/ ct32b1_cap0 33 [5] yes - i; pu r ? reserved. configure for an alternate function in the ioconfig block. i/o - pio1_0 ? general purpose digital input/output pin. i- ad1 ? a/d converter, input 1. i- ct32b1_cap0 ? capture input 0 for 32-bit timer 1. r/pio1_1/ad2/ ct32b1_mat0 34 [5] no - i; pu r ? reserved. configure for an alternate function in the ioconfig block. i/o - pio1_1 ? general purpose digital input/output pin. i- ad2 ? a/d converter, input 2. o- ct32b1_mat0 ? match output 0 for 32-bit timer 1. r/pio1_2/ad3/ ct32b1_mat1 35 [5] no - i; pu r ? reserved. configure for an alternate function in the ioconfig block. i/o - pio1_2 ? general purpose digital input/output pin. i- ad3 ? a/d converter, input 3. o- ct32b1_mat1 ? match output 1 for 32-bit timer 1. swdio/pio1_3/ ad4/ ct32b1_mat2 39 [5] no i/o i; pu swdio ? serial wire debug input/output. i/o - pio1_3 ? general purpose digital input/output pin. i- ad4 ? a/d converter, input 4. o- ct32b1_mat2 ? match output 2 for 32-bit timer 1. pio1_4/ad5/ ct32b1_mat3/ wakeup 40 [5] no i/o i; pu pio1_4 ? general purpose digital input/ output pin with 10 ns glitch filter. i- ad5 ? a/d converter, input 5. o- ct32b1_mat3 ? match output 3 for 32-bit timer 1. i- wakeup ? deep power-down mode wake-up pin with 20 ns glitch filter. this pin must be pulled high externally to enter deep power-down mode and pulled low to exit deep power-down mode. a low-going pulse as short as 50 ns wakes up the part. pio1_5/rts / ct32b0_cap0 45 [3] no i/o i; pu pio1_5 ? general purpose digital input/output pin. o- rts ? request to send output for uart. i- ct32b0_cap0 ? capture input 0 for 32-bit timer 0. pio1_6/rxd/ ct32b0_mat0 46 [3] no i/o i; pu pio1_6 ? general purpose digital input/output pin. i- rxd ? receiver input for uart. o- ct32b0_mat0 ? match output 0 for 32-bit timer 0. table 3. lpc11c12/c14 pin description table symbol pin start logic inputs type reset state [1] description
lpc11cx2_cx4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3.1 ? 15 may 2013 9 of 62 nxp semiconductors lpc11cx2/cx4 32-bit arm cortex-m0 microcontroller pio1_7/txd/ ct32b0_mat1 47 [3] no i/o i; pu pio1_7 ? general purpose digital input/output pin. o- txd ? transmitter output for uart. o- ct32b0_mat1 ? match output 1 for 32-bit timer 0. pio1_8/ ct16b1_cap0 9 [3] no i/o i; pu pio1_8 ? general purpose digital input/output pin. i- ct16b1_cap0 ? capture input 0 for 16-bit timer 1. pio1_9/ ct16b1_mat0 17 [3] no i/o i; pu pio1_9 ? general purpose digital input/output pin. o- ct16b1_mat0 ? match output 0 for 16-bit timer 1. pio1_10/ad6/ ct16b1_mat1 30 [5] no i/o i; pu pio1_10 ? general purpose digi tal input/output pin. i- ad6 ? a/d converter, input 6. o- ct16b1_mat1 ? match output 1 for 16-bit timer 1. pio1_11/ad7 42 [5] no i/o i; pu pio1_11 ? general purpose digital input/output pin. i- ad7 ? a/d converter, input 7. pio2_0 to pio2_11 port 2 ? port 2 is a 12-bit i/o port with individual direction and function controls for each bit. the operation of port 2 pins depends on the function selected through the ioconfig register block. pio2_0/dtr / ssel1 2 [3] no i/o i; pu pio2_0 ? general purpose digital input/output pin. i/o - dtr ? data terminal ready output for uart. i/o - ssel1 ? slave select for spi1. pio2_1/dsr /sck1 13 [3] no i/o i; pu pio2_1 ? general purpose digital input/output pin. i- dsr ? data set ready input for uart. i/o - sck1 ? serial clock for spi1. pio2_2/dcd / miso1 26 [3] no i/o i; pu pio2_2 ? general purpose digital input/output pin. i- dcd ? data carrier detect input for uart. i/o - miso1 ? master in slave out for spi1. pio2_3/ri /mosi1 38 [3] no i/o i; pu pio2_3 ? general purpose digital input/output pin. i- ri ? ring indicator input for uart. i/o - mosi1 ? master out slave in for spi1. pio2_4 18 [3] no i/o i; pu pio2_4 ? general purpose digital input/output pin. pio2_5 21 [3] no i/o i; pu pio2_5 ? general purpose digital input/output pin. pio2_6 1 [3] no i/o i; pu pio2_6 ? general purpose digital input/output pin. pio2_7 11 [3] no i/o i; pu pio2_7 ? general purpose digital input/output pin. pio2_8 12 [3] no i/o i; pu pio2_8 ? general purpose digital input/output pin. pio2_9 24 [3] no i/o i; pu pio2_9 ? general purpose digital input/output pin. pio2_10 25 [3] no i/o i; pu pio2_10 ? general purpose digi tal input/output pin. pio2_11/sck0 31 [3] no i/o i; pu pio2_11 ? general purpose digital input/output pin. i/o - sck0 ? serial clock for spi0. pio3_0 to pio3_3 port 3 ? port 3 is a 12-bit i/o port with individual direction and function controls for each bit. the operation of port 3 pins depends on the function selected through the ioconfig register block. pins pio3_4 to pio3_11 are not available. table 3. lpc11c12/c14 pin description table symbol pin start logic inputs type reset state [1] description
lpc11cx2_cx4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3.1 ? 15 may 2013 10 of 62 nxp semiconductors lpc11cx2/cx4 32-bit arm cortex-m0 microcontroller [1] pin state at reset for default function: i = input; o = ou tput; pu = internal pull-up enabled (pins pulled up to full v dd level); ia = inactive, no pull-up/down enabled. [2] 5 v tolerant pad. reset functionality is not available in deep power-down mode. use the wakeup pin to reset the chip and wake up from deep power-down mode. an external pull-up resistor is required on this pin for the deep power-down mode. see figure 26 for the reset pad configuration. [3] 5 v tolerant pad providing digital i/o functions with conf igurable pull-up/pull-down resistor s and configurable hysteresis ( see figure 25 ). [4] i 2 c-bus pads compliant with the i 2 c-bus specification for i 2 c standard mode and i 2 c fast-mode plus. [5] 5 v tolerant pad providing digital i/o functions with conf igurable pull-up/pull-down resistor s, configurable hysteresis, and analog input. when configured as a adc input, digital section of the pad is disabled and the pin is not 5 v tolerant (see figure 25 ). [6] 5 v tolerant digital i/o pad without pull-up/pull-down resistors. [7] when the system oscillator is not used, connect xtalin and xtalout as follows: xtalin can be left floating or can be grounde d (grounding is preferred to reduce susceptibilit y to noise). xtalout should be left floating. pio3_0/dtr 36 [3] no i/o i; pu pio3_0 ? general purpose digital input/output pin. o- dtr ? data terminal ready output for uart. pio3_1/dsr 37 [3] no i/o i; pu pio3_1 ? general purpose digital input/output pin. i- dsr ? data set ready input for uart. pio3_2/dcd 43 [3] no i/o i; pu pio3_2 ? general purpose digital input/output pin. i dcd ? data carrier detect input for uart. pio3_3/ri 48 [3] no i/o i; pu pio3_3 ? general purpose digital input/output pin. i- ri ? ring indicator input for uart. can_rxd 19 [6] no i i; ia can_rxd ? c_can receive data input. can_txd 20 [6] no o i; ia can_txd ? c_can transmit data output. v dd 8; 44 - i - supply voltage to the internal regulator, the external rail, and the adc. also used as the adc reference voltage. xtalin 6 [7] - i - input to the oscillator circuit and internal clock generator circuits. input voltage must not exceed 1.8 v. xtalout 7 [7] - o - output from the oscillator amplifier. v ss 5; 41 - i - ground. table 3. lpc11c12/c14 pin description table symbol pin start logic inputs type reset state [1] description table 4. lpc11c22/c24 pin description table symbol pin start logic inputs type reset state [1] description pio0_0 to pio0_11 port 0 ? port 0 is a 12-bit i/o port with individual direction and function controls for each bit. the operation of port 0 pins depends on the function selected through the ioconfig register block. reset /pio0_0 3 [2] yes i i; pu reset ? external reset input with 20 ns glitch filter. a low-going pulse as short as 50 ns on this pin resets the device, causing i/o ports and peripherals to take on their default states, and processor execution to begin at address 0. i/o - pio0_0 ? general purpose digital input/ output pin with 10 ns glitch filter.
lpc11cx2_cx4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3.1 ? 15 may 2013 11 of 62 nxp semiconductors lpc11cx2/cx4 32-bit arm cortex-m0 microcontroller pio0_1/clkout/ ct32b0_mat2 4 [3] yes i/o i; pu pio0_1 ? general purpose digital input/ output pin. a low level on this pin during reset starts the flash isp command handler via uart (if pio0_3 is high) or via c_can (if pio0_3 is low). o- clkout ? clockout pin. o- ct32b0_mat2 ? match output 2 for 32-bit timer 0. pio0_2/ssel0/ ct16b0_cap0 10 [3] yes i/o i; pu pio0_2 ? general purpose digital input/output pin. i/o - ssel0 ? slave select for spi0. i- ct16b0_cap0 ? capture input 0 for 16-bit timer 0. pio0_3 14 [3] yes i/o i; pu pio0_3 ? general purpose digital input/output pin. this pin is monitored during reset: together with a low level on pin pio0_1, a low level starts the flash isp command handler via c_can and a high level starts the flash isp command handler via uart. pio0_4/scl 15 [4] yes i/o i; ia pio0_4 ? general purpose digital input/output pin (open-drain). i/o - scl ? i 2 c-bus, open-drain clock input/output. high-current sink only if i 2 c fast-mode plus is selected in the i/o configuration register. pio0_5/sda 16 [4] yes i/o i; ia pio0_5 ? general purpose digital input/output pin (open-drain). i/o - sda ? i 2 c-bus, open-drain data input/ou tput. high-current sink only if i 2 c fast-mode plus is selected in the i/o configuration register. pio0_6/sck0 23 [3] yes i/o i; pu pio0_6 ? general purpose digital input/output pin. i/o - sck0 ? serial clock for spi0. pio0_7/cts 24 [3] yes i/o i; pu pio0_7 ? general purpose digital input/output pin (high-current output driver). i- cts ? clear to send input for uart. pio0_8/miso0/ ct16b0_mat0 27 [3] yes i/o i; pu pio0_8 ? general purpose digital input/output pin. i/o - miso0 ? master in slave out for spi0. o- ct16b0_mat0 ? match output 0 for 16-bit timer 0. pio0_9/mosi0/ ct16b0_mat1 28 [3] yes i/o i; pu pio0_9 ? general purpose digital input/output pin. i/o - mosi0 ? master out slave in for spi0. o- ct16b0_mat1 ? match output 1 for 16-bit timer 0. swclk/pio0_10/ sck0/ ct16b0_mat2 29 [3] yes i i; pu swclk ? serial wire clock. i/o - pio0_10 ? general purpose digi tal input/output pin. i/o - sck0 ? serial clock for spi0. o- ct16b0_mat2 ? match output 2 for 16-bit timer 0. r/pio0_11/ ad0/ ct32b0_mat3 32 [5] yes - i; pu r ? reserved. configure for an alternate function in the ioconfig block. i/o - pio0_11 ? general purpose digital input/output pin. i- ad0 ? a/d converter, input 0. o- ct32b0_mat3 ? match output 3 for 32-bit timer 0. pio1_0 to pio1_11 port 1 ? port 1 is a 12-bit i/o port with individual direction and function controls for each bit. the operation of port 1 pins depends on the function selected through the ioconfig register block. table 4. lpc11c22/c24 pin description table symbol pin start logic inputs type reset state [1] description
lpc11cx2_cx4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3.1 ? 15 may 2013 12 of 62 nxp semiconductors lpc11cx2/cx4 32-bit arm cortex-m0 microcontroller r/pio1_0/ad1/ ct32b1_cap0 33 [5] yes - i; pu r ? reserved. configure for an alternate function in the ioconfig block. i/o - pio1_0 ? general purpose digital input/output pin. i- ad1 ? a/d converter, input 1. i- ct32b1_cap0 ? capture input 0 for 32-bit timer 1. r/pio1_1/ad2/ ct32b1_mat0 34 [5] no - i; pu r ? reserved. configure for an alternate function in the ioconfig block. i/o - pio1_1 ? general purpose digital input/output pin. i- ad2 ? a/d converter, input 2. o- ct32b1_mat0 ? match output 0 for 32-bit timer 1. r/pio1_2/ad3/ ct32b1_mat1 35 [5] no - i; pu r ? reserved. configure for an alternate function in the ioconfig block. i/o - pio1_2 ? general purpose digital input/output pin. i- ad3 ? a/d converter, input 3. o- ct32b1_mat1 ? match output 1 for 32-bit timer 1. swdio/pio1_3/ ad4/ ct32b1_mat2 39 [5] no i/o i; pu swdio ? serial wire debug input/output. i/o - pio1_3 ? general purpose digital input/output pin. i- ad4 ? a/d converter, input 4. o- ct32b1_mat2 ? match output 2 for 32-bit timer 1. pio1_4/ad5/ ct32b1_mat3/ wakeup 40 [5] no i/o i; pu pio1_4 ? general purpose digital input/ output pin with 10 ns glitch filter. i- ad5 ? a/d converter, input 5. o- ct32b1_mat3 ? match output 3 for 32-bit timer 1. i- wakeup ? deep power-down mode wake-up pin with 20 ns glitch filter. this pin must be pulled high externally to enter deep power-down mode and pulled low to exit deep power-down mode. a low-going pulse as short as 50 ns wakes up the part. pio1_5/rts / ct32b0_cap0 45 [3] no i/o i; pu pio1_5 ? general purpose digital input/output pin. o- rts ? request to send output for uart. i- ct32b0_cap0 ? capture input 0 for 32-bit timer 0. pio1_6/rxd/ ct32b0_mat0 46 [3] no i/o i; pu pio1_6 ? general purpose digital input/output pin. i- rxd ? receiver input for uart. o- ct32b0_mat0 ? match output 0 for 32-bit timer 0. pio1_7/txd/ ct32b0_mat1 47 [3] no i/o i; pu pio1_7 ? general purpose digital input/output pin. o- txd ? transmitter output for uart. o- ct32b0_mat1 ? match output 1 for 32-bit timer 0. pio1_8/ ct16b1_cap0 9 [3] no i/o i; pu pio1_8 ? general purpose digital input/output pin. i- ct16b1_cap0 ? capture input 0 for 16-bit timer 1. pio1_10/ad6/ ct16b1_mat1 30 [5] no i/o i; pu pio1_10 ? general purpose digi tal input/output pin. i- ad6 ? a/d converter, input 6. o- ct16b1_mat1 ? match output 1 for 16-bit timer 1. table 4. lpc11c22/c24 pin description table symbol pin start logic inputs type reset state [1] description
lpc11cx2_cx4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3.1 ? 15 may 2013 13 of 62 nxp semiconductors lpc11cx2/cx4 32-bit arm cortex-m0 microcontroller pio1_11/ad7 42 [5] no i/o i; pu pio1_11 ? general purpose digital input/output pin. i- ad7 ? a/d converter, input 7. pio2_0 to pio2_11 port 2 ? port 2 is a 12-bit i/o port with individual direction and function controls for each bit. the operation of port 2 pins depends on the function selected through the ioconfig register block. pio2_0/dtr / ssel1 2 [3] no i/o i; pu pio2_0 ? general purpose digital input/output pin. i/o - dtr ? data terminal ready output for uart. i/o - ssel1 ? slave select for spi1. pio2_1/dsr /sck1 13 [3] no i/o i; pu pio2_1 ? general purpose digital input/output pin. i- dsr ? data set ready input for uart. i/o - sck1 ? serial clock for spi1. pio2_2/dcd / miso1 26 [3] no i/o i; pu pio2_2 ? general purpose digital input/output pin. i- dcd ? data carrier detect input for uart. i/o - miso1 ? master in slave out for spi1. pio2_3/ri /mosi1 38 [3] no i/o i; pu pio2_3 ? general purpose digital input/output pin. i- ri ? ring indicator input for uart. i/o - mosi1 ? master out slave in for spi1. pio2_6 1 [3] no i/o i; pu pio2_6 ? general purpose digital input/output pin. pio2_7 11 [3] no i/o i; pu pio2_7 ? general purpose digital input/output pin. pio2_8 12 [3] no i/o i; pu pio2_8 ? general purpose digital input/output pin. pio2_10 25 [3] no i/o i; pu pio2_10 ? general purpose digi tal input/output pin. pio2_11/sck0 31 [3] no i/o i; pu pio2_11 ? general purpose digital input/output pin. i/o - sck0 ? serial clock for spi0. pio3_0 to pio3_3 port 3 ? port 3 is a 12-bit i/o port with individual direction and function controls for each bit. the operation of port 3 pins depends on the function selected through the ioconfig register block. pins pio3_4 to pio3_11 are not available. pio3_0/dtr 36 [3] no i/o i; pu pio3_0 ? general purpose digital input/output pin. o- dtr ? data terminal ready output for uart. pio3_1/dsr 37 [3] no i/o i; pu pio3_1 ? general purpose digital input/output pin. i- dsr ? data set ready input for uart. pio3_2/dcd 43 [3] no i/o i; pu pio3_2 ? general purpose digital input/output pin. i dcd ? data carrier detect input for uart. pio3_3/ri 48 [3] no i/o i; pu pio3_3 ? general purpose digital input/output pin. i- ri ? ring indicator input for uart. canl 18 no i/o - low-level can bus line. canh 19 no i/o - high-level can bus line. stb 22 no i - silent mode control input for can transceiver (low = normal mode, high = silent mode). vdd_can 17 - - - supply voltage for i/o level of can transceiver. v cc 20 - - - supply voltage for can transceiver. table 4. lpc11c22/c24 pin description table symbol pin start logic inputs type reset state [1] description
lpc11cx2_cx4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3.1 ? 15 may 2013 14 of 62 nxp semiconductors lpc11cx2/cx4 32-bit arm cortex-m0 microcontroller [1] pin state at reset for default function: i = input; o = ou tput; pu = internal pull-up enabled (pins pulled up to full v dd level); ia = inactive, no pull-up/down enabled. [2] 5 v tolerant pad. reset functionality is not available in deep power-down mode. use the wakeup pin to reset the chip and wake up from deep power-down mode. an external pull-up resistor is required on this pin for the deep power-down mode. see figure 26 for the reset pad configuration. [3] 5 v tolerant pad providing digital i/o functions with conf igurable pull-up/pull-down resistor s and configurable hysteresis ( see figure 25 ). [4] i 2 c-bus pads compliant with the i 2 c-bus specification for i 2 c standard mode and i 2 c fast-mode plus. [5] 5 v tolerant pad providing digital i/o functions with conf igurable pull-up/pull-down resistor s, configurable hysteresis, and analog input. when configured as a adc input, digital section of the pad is disabled and the pin is not 5 v tolerant (see figure 25 ). [6] 5 v tolerant digital i/o pad without pull-up/pull-down resistors. [7] when the system oscillator is not used, connect xtalin and xtalout as follows: xtalin can be left floating or can be grounde d (grounding is preferred to reduce susceptibilit y to noise). xtalout should be left floating. gnd 21 - - - ground for can transceiver. v dd 8; 44 - i - supply voltage to the internal regulator, the external rail, and the adc. also used as the adc reference voltage. xtalin 6 [7] - i - input to the oscillator circuit and internal clock generator circuits. input voltage must not exceed 1.8 v. xtalout 7 [7] - o - output from the oscillator amplifier. v ss 5; 41 - i - ground. table 4. lpc11c22/c24 pin description table symbol pin start logic inputs type reset state [1] description
lpc11cx2_cx4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3.1 ? 15 may 2013 15 of 62 nxp semiconductors lpc11cx2/cx4 32-bit arm cortex-m0 microcontroller 7. functional description 7.1 arm cortex-m0 processor the arm cortex-m0 is a general purpose, 32-bit microprocessor, which offers high performance and very low power consumption. 7.2 on-chip flash program memory the lpc11cx2/cx4 contain 32 kb (lpc11c14/c24) or 16 kb (lpc11c12/c22) of on-chip flash program memory. 7.3 on-chip sram the lpc11cx2/cx4 contain a total of 8 kb on-chip static ram data memory. 7.4 memory map the lpc11cx2/cx4 incorporates several distinct memory regions, shown in the following figures. figure 4 shows the overall map of the entire address space from the user program viewpoint following reset. the interrupt vector area supports address remapping. the ahb peripheral area is 2 megabyte in si ze, and is divided to allow for up to 128 peripherals. the apb peripheral ar ea is 512 kb in size and is divided to allow for up to 32 peripherals. each peripheral of either type is allocated 16 kilobytes of space. this allows simplifying the address decoding for each peripheral.
lpc11cx2_cx4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3.1 ? 15 may 2013 16 of 62 nxp semiconductors lpc11cx2/cx4 32-bit arm cortex-m0 microcontroller 7.5 nested vectored inte rrupt controller (nvic) the nested vectored in terrupt controller (nvic) is an integral part of the cortex-m0. the tight coupling to the cpu allows for low interr upt latency and efficient processing of late arriving interrupts. 7.5.1 features ? controls system exceptions and peripheral interrupts. ? in the lpc11cx2/cx4, the nvic supports 32 vectored interrupts including 13 inputs to the start logic from individual gpio pins. fig 4. lpc11cx2/cx4 memory map 0x5000 0000 0x5001 0000 0x5002 0000 0x5020 0000 ahb peripherals 16 - 127 reserved gpio pio1 4-7 0x5003 0000 0x5004 0000 gpio pio2 gpio pio3 8-11 12-15 gpio pio0 0-3 apb peripherals 0x4000 4000 0x4000 8000 0x4000 c000 0x4001 0000 0x4001 8000 0x4002 0000 0x4002 8000 0x4003 8000 0x4003 c000 0x4004 0000 0x4004 4000 0x4004 8000 0x4004 c000 0x4005 0000 0x4005 4000 0x4005 8000 0x4005 c000 0x4008 0000 0x4002 4000 0x4001 c000 0x4001 4000 0x4000 0000 wdt 32-bit counter/timer 0 32-bit counter/timer 1 adc uart pmu i 2 c-bus 10 - 13 reserved reserved reserved reserved 23 - 31 reserved 0 1 2 3 4 5 6 7 8 9 16 15 14 17 18 reserved reserved reserved 0x0000 0000 0 gb 0.5 gb 4 gb 1 gb 0x1000 2000 0x1fff 0000 0x1fff 4000 0x2000 0000 0x4000 0000 0x4008 0000 0x5000 0000 0x5020 0000 0xffff ffff reserved reserved reserved apb peripherals ahb peripherals 0x1000 0000 8 kb sram lpc11cx2/cx4 0x0000 4000 16 kb on-chip flash (lpc11cx2) 0x0000 8000 32 kb on-chip flash (lpc11cx4) 16 kb boot rom 0x0000 0000 0x0000 00c0 active interrupt vectors 002aaf268 reserved spi0 16-bit counter/timer 1 16-bit counter/timer 0 ioconfig system control 20 19 c_can reserved 22 21 spi1 flash controller 0xe000 0000 0xe010 0000 private peripheral bus
lpc11cx2_cx4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3.1 ? 15 may 2013 17 of 62 nxp semiconductors lpc11cx2/cx4 32-bit arm cortex-m0 microcontroller ? four programmable interrupt priority leve ls, with hardware pr iority level masking. ? software interr upt generation. 7.5.2 interrupt sources each peripheral device has one interrupt line connected to the nvic but may have several interrupt flags. individual interrupt flags may also represent more than one interrupt source. any gpio pin (total of 40 pins (lpc11c12/c14) or 36 pins (lpc11c22/c24)) regardless of the selected function, can be programmed to generate an interrupt on a level, or rising edge or falling edge, or both. 7.6 ioconfig block the ioconfig block allows sele cted pins of the microcontroller to have more than one function. configuration registers control the multiplexers to allow connection between the pin and the on-chip peripherals. peripherals should be connected to the appropriate pins prior to being activated and prior to any related interrupt(s) being enabled. activi ty of any enabled peripheral function that is not mapped to a related pin should be considered undefined. 7.7 fast general purpose parallel i/o device pins that are not connec ted to a specific peripheral function are controlled by the gpio registers. pins may be dynamically configured as inputs or outputs. multiple outputs can be set or cleared in one write operation. lpc11cx2/cx4 use accelerated gpio functions: ? gpio registers are a dedicated ahb peripheral so that the fastest possible i/o timing can be achieved. ? entire port value can be written in one instruction. additionally, any gpio pin (total of 40 pins (lpc11c12/c14) or 36 pins (lpc11c22/c24)) providing a digital function can be programmed to generate an interrupt on a level, a rising or falling edge, or both. 7.7.1 features ? bit level port registers allow a single instruct ion to set or clear any number of bits in one write operation. ? direction control of individual bits. ? all gpio pins default to inputs with pull-ups enabled after reset except for the i 2 c-bus true open-drain pins pio0_4 and pio0_5. ? pull-up/pull-down resistor configuration can be programmed through the ioconfig block for each gpio pin (except pio0_4 and pio0_5). ? all gpio pins (except pio0_4 and pio0_5) are pulled up to 3.3 v (v dd = 3.3 v) if their pull-up resistor is enabled in the ioconfig block.
lpc11cx2_cx4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3.1 ? 15 may 2013 18 of 62 nxp semiconductors lpc11cx2/cx4 32-bit arm cortex-m0 microcontroller 7.8 uart the lpc11cx2/cx4 contain one uart. support for rs-485/9-bit mode allows both software address detection and automatic address detection using 9-bit mode. the uart includes a fractional baud rate generator. standard baud rates such as 115200 bd can be achieved with any crystal frequency above 2 mhz. 7.8.1 features ? maximum uart data bit rate of 3.125 mbit/s. ? 16 byte receive and transmit fifos. ? register locations conform to 16c550 industry standard. ? receiver fifo trigger points at 1 b, 4 b, 8 b, and 14 b. ? built-in fractional baud rate generator cove ring wide range of baud rates without a need for external crystals of particular values. ? fifo control mechanism that enables software flow control implementation. ? support for rs-485/9-bit mode. ? support for modem control. 7.9 spi serial i/o controller the lpc11cx2/cx4 contain two spi controllers. both spi controllers support ssp features. the spi controller is capable of operation on a ssp, 4-wire ssi, or microwire bus. it can interact with multiple masters and slaves on the bus. only a single master and a single slave can communicate on the bus during a given data transfer. the spi supports full duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the slave and from the slave to the master. in practice, often only one of these data flows carries meaningful data. 7.9.1 features ? maximum spi speed of 25 mbit/s (master) or 4.17 mbit/s (slave) (in ssp mode) ? compatible with motorola spi, 4-wire texas instruments ssi, and national semiconductor microwire buses ? synchronous serial communication ? master or slave operation ? 8-frame fifos for both transmit and receive ? 4-bit to 16-bit frame 7.10 i 2 c-bus serial i/o controller the lpc11cx2/cx4 contain one i 2 c-bus controller.
lpc11cx2_cx4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3.1 ? 15 may 2013 19 of 62 nxp semiconductors lpc11cx2/cx4 32-bit arm cortex-m0 microcontroller the i 2 c-bus is bidirectional for inter-ic contro l using only two wires: a serial clock line (scl) and a serial data line (sda). each de vice is recognized by a unique address and can operate as either a receiver-only device (e.g., an lcd driver) or a transmitter with the capability to both receive and send information (such as me mory). transmitters and/or receivers can operate in either master or sl ave mode, depending on whether the chip has to initiate a data transfer or is only addressed. the i 2 c is a multi-master bus and can be controlled by more than one bus master connected to it. 7.10.1 features ? the i 2 c-interface is a standard i 2 c-bus compliant interface with open-drain pins. the i 2 c-bus interface also supports fast-mod e plus with bit rates up to 1 mbit/s. ? easy to configure as master, slave, or master/slave. ? programmable clocks allow versatile rate control. ? bidirectional data transfer between masters and slaves. ? multi-master bus (no central master). ? arbitration between simultaneously transmit ting masters without corruption of serial data on the bus. ? serial clock synchronization allows devices with different bit rates to communicate via one serial bus. ? serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer. ? the i 2 c-bus can be used for test and diagnostic purposes. ? the i 2 c-bus controller supports multiple address recognition and a bus monitor mode. 7.11 c_can controller controller area network (can) is the definition of a high performance communication protocol for serial data communication. the c_ can controller is designed to provide a full implementation of the can protocol accordin g to the can specification version 2.0b. the c_can controller allows to build powerful local networks with low-cost multiplex wiring by supporting distributed real-time control with a very high level of security. on-chip c_can drivers provide an api for initialization and commu nication using can and canopen standards. 7.11.1 features ? conforms to protocol version 2.0 parts a and b. ? supports bit rate of up to 1 mbit/s. ? supports 32 message objects. ? each message object has its own identifier mask. ? provides programmable fifo mode (concatenation of message objects). ? provides maskable interrupts. ? supports disabled automatic retransmission (dar) mode for time-triggered can applications. ? provides programmable loop-back mode for self-test operation.
lpc11cx2_cx4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3.1 ? 15 may 2013 20 of 62 nxp semiconductors lpc11cx2/cx4 32-bit arm cortex-m0 microcontroller ? the c_can api includes the following functions: ? c_can set-up and initialization ? c_can send and receive messages ? c_can status ? canopen object dictionary ? canopen sdo expedited communication ? canopen sdo segmented co mmunication primitives ? canopen sdo fall-back handler ? flash isp programming via c_can supported. 7.11.2 on-chip, high-speed can transceiver remark: the on-chip can transceiver is available on parts lpc11c22/c24 only. compared to the lpc11c12/c14, the lpc11c22/c24 supports fewer gpio functions, and in addition, one counter/timer match function is removed to allow interfacing the can high-speed transceiver to the can bus. see table 4 and figure 1 . 7.11.2.1 features ? data rates of up to 1 mbit/s ? fully iso 11898-2 compliant ? undervoltage detection and thermal protection ? low electromagnetic emission (eme) and high electromagnetic immunity (emi) 7.11.2.2 normal mode a low level on pin stb selects normal mode. in this mode, the transceiver is able to transmit and receive data via the bus lines canh and canl (see figure 28 ). the differential receiver converts the analog data on the bus lines into digital data which are received by the can_rxd inpu t of the c_can controller. 7.11.2.3 silent mode a high level on pin stb selects silent mode. in silent mode the tran smitter is disabled, releasing the bus pins to recessive state. all other functions, including the receiver, continue to operate as in normal mode. silent mode can be used to prevent a faulty c_can controller from disrupting all network communications. 7.11.2.4 undervoltage protection should v cc or vdd_can drop below their respective undervoltage detection levels (v uvd(vcc) and v uvd (vdd_can) ; see ta b l e 8 ), the transceiver will switch off and disengage from the bus (zero load) until v cc and vdd_can have recovered. 7.11.2.5 thermal protection the output drivers are protected against overte mperature conditions. if the virtual junction temperature exceeds the shutdo wn junction temperature, t j(sd) (see ta b l e 8 ), the output drivers will be disabled unt il the virtual junction te mperature falls below t j(sd) .
lpc11cx2_cx4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3.1 ? 15 may 2013 21 of 62 nxp semiconductors lpc11cx2/cx4 32-bit arm cortex-m0 microcontroller 7.11.2.6 time-out function a ?txd dominant time-out? timer is star ted when the can_txd signal of the c_can controller is set low. if the low state on the can_txd signal persists for longer than t to(dom)txd , the transmitter is disabled, releasing th e bus lines to recessive state. this function prevents a hardware and/or software application failure from driving the bus lines to a permanent dominant state (blocking all network communications). the txd dominant time-out timer is reset when the can_txd signal is set high. the txd dominant time-out time also defines the minimum possible bit rate of 40 kbit/s. 7.12 10-bit adc the lpc11cx2/cx4 contains one adc. the adc is a single 10-bit successive approximation adc with eight channels. 7.12.1 features ? 10-bit successive approximation adc. ? input multiplexing among 8 pins. ? power-down mode. ? measurement range 0 v to v dd . ? 10-bit conversion time ? 2.44 ? s (up to 400 ksamples/s). ? burst conversion mode for single or multiple inputs. ? optional conversion on transition of input pin or timer match signal. ? individual result registers for each adc channel to reduce interrupt overhead. 7.13 general purpose externa l event counter/timers the lpc11cx2/cx4 includes two 32-bit counter/timers and two 16-bit counter/timers. the counter/timer is designed to count cycles of the system derived clock. it can optionally generate interrupts or perform other actions at specified timer values, based on four match registers. each counter/timer also incl udes one capture input to trap the timer value when an input signal transitions, optionally generating an interrupt. 7.13.1 features ? a 32-bit/16-bit timer/counter with a programmable 32-bit/16-bit prescaler. ? counter or timer operation. ? one capture channel per timer, that can ta ke a snapshot of the timer value when an input signal transitions. a capture event may also generate an interrupt. ? four match registers per timer that allow: ? continuous operation with optional interrupt generation on match. ? stop timer on match with optional interrupt generation. ? reset timer on match with optional interrupt generation. ? up to four external outputs corresponding to match registers, with the following capabilities: ? set low on match. ? set high on match.
lpc11cx2_cx4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3.1 ? 15 may 2013 22 of 62 nxp semiconductors lpc11cx2/cx4 32-bit arm cortex-m0 microcontroller ? toggle on match. ? do nothing on match. 7.14 system tick timer the arm cortex-m0 includes a system tick timer (systic k) that is inte nded to generate a dedicated systick exception at a fi xed time interval (typically 10 ms). 7.15 watchdog timer the purpose of the watchdog is to reset t he microcontroller within a selectable time period. 7.15.1 features ? internally resets chip if not period ically reloaded. ? debug mode. ? enabled by software but requires a hardware reset or a watchdog reset/interrupt to be disabled. ? incorrect/incomplete feed sequence causes reset/interrupt if enabled. ? flag to indicate watchdog reset. ? programmable 24-bit timer with internal prescaler. ? selectable time period from (t cy(wdclk) ? 256 ? 4) to (t cy(wdclk) ? 2 24 ? 4) in multiples of t cy(wdclk) ? 4. ? the watchdog clock (wdclk) source can be selected from the in ternal rc oscillator (irc), the watchdog oscillator, or the main cl ock. this gives a wid e range of potential timing choices of watchdog operation unde r different power reduction conditions. it also provides the ability to run the wdt from an entirely internal source that is not dependent on an external crystal and its associated components and wiring for increased reliability. 7.16 clocking and power control 7.16.1 crystal oscillators the lpc11cx2/cx4 include three independent oscillato rs. these are the system oscillator, the internal rc oscillator (irc), and the watchdog os cillator. each oscillator can be used for more than one purpose as required in a particular application. following reset, the lpc11cx2/cx4 will operat e from the internal rc oscillator until switched by software. this a llows systems to operate without any external crystal and the bootloader code to operate at a known frequency. see figure 5 for an overview of the lpc11cx2/cx4 clock generation.
lpc11cx2_cx4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3.1 ? 15 may 2013 23 of 62 nxp semiconductors lpc11cx2/cx4 32-bit arm cortex-m0 microcontroller 7.16.1.1 internal rc oscillator the irc may be used as the clock source for th e wdt, and/or as the clock that drives the pll and subsequently the cpu. the nominal irc frequency is 12 mhz. the irc is trimmed to 1 % accuracy over the entire voltage and temperature range. upon power-up or any chip reset, the lpc11cx2/cx4 use the irc as the clock source. software may later switch to one of the other available clock sources. 7.16.1.2 system oscillator the system oscillator can be used as the clock source for the cpu, with or without using the pll. the system oscillator operates at frequencies of 1 mhz to 25 mhz. this frequency can be boosted to a higher frequency, up to the maximum cpu operating frequency, by the system pll. fig 5. lpc11cx2/cx4 clock generation block diagram system pll irc oscillator system oscillator watchdog oscillator irc oscillator watchdog oscillator mainclksel (main clock select) syspllclksel (system pll clock select) system clock divider ahb clock 0 (system) sysahbclkctrl[1:18] (ahb clock enable) ahb clocks 1 to 18 (memories and peripherals) spi0 peripheral clock divider spi0 spi1 peripheral clock divider spi1 uart peripheral clock divider uart wdt clock divider wdt wdtuen (wdt clock update enable) watchdog oscillator irc oscillator system oscillator clkout pin clock divider clkout pin clkoutuen (clkout update enable) 002aae514 main clock system clock irc oscillator 18
lpc11cx2_cx4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3.1 ? 15 may 2013 24 of 62 nxp semiconductors lpc11cx2/cx4 32-bit arm cortex-m0 microcontroller 7.16.1.3 watchdog oscillator the watchdog oscillator can be used as a clock source that directly drives the cpu, the watchdog timer, or the clkout pin. the watchdog oscillator nominal frequency is programmable between 7.8 khz and 1.7 mhz. th e frequency spread over processing and temperature is ? 40 % (see ta b l e 1 5 ). 7.16.2 system pll the pll accepts an input clock frequency in the range of 10 mhz to 25 mhz. the input frequency is multiplied up to a high frequency with a curren t controlled oscillator (cco). the multiplier can be an integer value from 1 to 32. the cco operates in the range of 156 mhz to 320 mhz, so there is an additional divider in the loop to keep the cco within its frequency range while the pll is provid ing the desired output frequency. the output divider may be set to divide by 2, 4, 8, or 16 to produce the output clock. the pll output frequency must be lower than 100 mhz. since th e minimum output divider value is 2, it is insured that the pll output has a 50 % duty cycle. the pll is turned off and bypassed following a chip reset and may be enabled by software. the program must configure and activate the pll, wait for the pll to lock, and then connect to the pll as a clock source. the pll settling time is 100 ? s. 7.16.3 clock output the lpc11cx2/cx4 features a cl ock output function that routes the irc oscillator, the system oscillator, the watchdog oscillator, or the main clock to an output pin. 7.16.4 wake-up process the lpc11cx2/cx4 begin operation at power-up and when awakened from deep power-down mode by using the 12 mhz irc o scillator as the clock source. this allows chip operation to resume quickly. if the syst em oscillator or the pll is needed by the application, software will need to enable these features an d wait for them to stabilize before they are used as a clock source. 7.16.5 power control the lpc11cx2/cx4 support a variety of powe r control features. there are three special modes of processor power reduction: sleep mode, deep-sleep mode, and deep power-down mode. the cpu clock rate may also be controlled as needed by changing clock sources, reconfiguring pll values, and/or altering the cpu clock divider value. this allows a trade-off of power versus processing speed based on application requirements. in addition, a register is pr ovided for shutting down the cl ocks to individual on-chip peripherals, allowing fine tuning of power consumption by eliminating all dynamic power use in any peripherals that are not required fo r the application. selected peripherals have their own clock divider which prov ides even better power control. 7.16.5.1 sleep mode when sleep mode is entered, the clock to the core is stopped. resumption from the sleep mode does not need any special sequence but re-enabling the clock to the arm core. in sleep mode, execution of instructions is suspended until either a reset or interrupt occurs. peripheral functions continue opera tion during sleep mode and may generate interrupts to cause the processor to resume execution. sleep mode eliminates dynamic power used by the processor itself, memory systems and related controllers, and internal buses.
lpc11cx2_cx4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3.1 ? 15 may 2013 25 of 62 nxp semiconductors lpc11cx2/cx4 32-bit arm cortex-m0 microcontroller 7.16.5.2 deep-sleep mode in deep-sleep mode, the chip is in sleep mode, and in addition all analog blocks are shut down. as an exception, the user has the opt ion to keep the watchdog oscillator and the bod circuit running for self-timed wake-up and bod protection. deep-sleep mode allows for additional power savings. up to 13 pins total, see ta b l e 3 , serve as external wake-up pins to a dedicated start logic to wake up the chip from deep-sleep mode. unless the watchdog oscillator is selected to run in deep-s leep mode, the clock source should be switched to irc before entering deep-sleep mode, because the irc can be switched on and off glitch-free. 7.16.5.3 deep power-down mode in deep power-down mode, power is shut off to the entire chip with the exception of the wakeup pin. the lpc11cx2/c x4 can wake up from d eep power-down mode via the wakeup pin. when entering deep power-down mode, an external pull-up resistor is required on the wakeup pin to hold it high. the reset pin must also be held high to prevent it from floating while in deep power-down mode. 7.17 system control 7.17.1 start logic the start logic connects external pins to corresponding interrupts in the nvic. each pin shown in ta b l e 3 as input to the start logic has an individual interrupt in the nvic interrupt vector table. the start logic pins can serve as external interrupt pins when the chip is running. in addition, an input signal on the start logic pins can wake up the chip from deep-sleep mode when all clocks are shut down. the start logic must be configured in the system configuration block and in the nvic before being used. 7.17.2 reset reset has four so urces on the lpc11cx2/cx4: the reset pin, the watchdog reset, power-on reset (por), and the browno ut detection (bod) circuit. the reset pin is a schmitt trigger input pin. assertion of chip re set by any source, once the operating voltage attains a usable level, starts the irc and initializes the flash controller. when the internal reset is removed, the proc essor begins executing at address 0, which is initially the reset vector mapped from the bo ot block. at that point, all of the processor and peripheral registers have been in itialized to predetermined values. an external pull-up resistor is required on the reset pin if deep power-down mode is used. 7.17.3 brownout detection the lpc11cx2/cx4 includes four levels for monitoring the voltage on the v dd pin. if this voltage falls below one of the four selected levels, the bod asserts an interrupt signal to the nvic. this signal can be enabled for inte rrupt in the interrupt enable register in the
lpc11cx2_cx4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3.1 ? 15 may 2013 26 of 62 nxp semiconductors lpc11cx2/cx4 32-bit arm cortex-m0 microcontroller nvic in order to cause a cpu in terrupt; if not, software can monitor the signal by reading a dedicated status register. four additional threshold levels can be selected to cause a forced reset of the chip. 7.17.4 code security (code read protection - crp) this feature of the lpc11cx2/cx4 allows user to enable different levels of security in the system so that access to the on-chip flash and use of the serial wire debugger (swd) and in-system programming (isp) can be restricted. when needed, crp is invoked by programming a specific pattern into a ded icated flash location. iap commands are not affected by the crp. in addition, isp entry via the pio0_1 pin can be disabled without enabling crp. for details see the lpc11cx user manual . there are three levels of code read protection: 1. crp1 disables access to the chip via the swd and allows partial flash update (excluding flash sector 0) using a limited set of the isp commands. this mode is useful when crp is required and flash fi eld updates are needed but all sectors can not be erased. 2. crp2 disables access to the chip via the swd and only allows full flash erase and update using a reduced set of the isp commands. 3. running an application with level crp3 select ed fully disables any access to the chip via the swd pins and the isp. this mode effectively disables isp override using pio0_1 pin, too. it is up to the user?s application to provide (if needed) flash update mechanism using iap calls or call reinvoke isp command to enable flash update via the uart. in addition to the three crp levels, sampli ng of pin pio0_1 for valid user code can be disabled. for details see the lpc11cx user manual . 7.17.5 bootloader the bootloader controls initial operation after reset and also provides the means to program the flash memory. this could be init ial programming of a blank device, erasure and re-programming of a previously programmed device, or programming of the flash memory by the application program in a running system. the bootloader code is executed every time th e part is reset or powered up. the loader can either execute the user application code or the isp command handler via uart or c_can. a low level during reset applied to the pio0_1 pin is considered as an external hardware request to start the isp command handler. the state of pio0_3 at reset determines whether the uart (pio0_3 high) or the c_ca n (pio0_3 low) interface will be used. caution if level three code read protection (crp3) is selected, no future factory testing can be performed on the device.
lpc11cx2_cx4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3.1 ? 15 may 2013 27 of 62 nxp semiconductors lpc11cx2/cx4 32-bit arm cortex-m0 microcontroller the c_can isp command handler uses the canopen protocol and data organization method. c_can isp commands have the sa me functionality as uart isp commands. 7.17.6 apb interface the apb peripherals are located on one apb bus. 7.17.7 ahblite the ahblite connects the cpu bus of the arm cortex-m0 to the flash memory, the main static ram, and the boot rom. 7.17.8 external interrupt inputs all gpio pins can be level or edge sensitive interrupt inputs. in addition, start logic inputs serve as external interrupts (see section 7.17.1 ). 7.18 emulation and debugging debug functions are integrated into the arm cortex-m0. serial wire debug with four breakpoints and two watchpoints is supported.
lpc11cx2_cx4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3.1 ? 15 may 2013 28 of 62 nxp semiconductors lpc11cx2/cx4 32-bit arm cortex-m0 microcontroller 8. limiting values [1] the following applies to the limiting values: a) this product includes circuitry specif ically designed for the protection of its in ternal devices from the damaging effects of excessive static charge. nonetheless, it is sugges ted that conventional precautions be tak en to avoid applying greater than the rated maximum. b) parameters are valid over operating te mperature range unless otherwise specifi ed. all voltages are with respect to v ss unless otherwise noted. [2] maximum/minimum voltage above the maximum operating voltage (see table 6 ) and below ground that can be applied for a short time (<10 ms) to a device without leading to irrecoverable failure. fa ilure includes the loss of reli ability and shorter lifetime of the device. [3] including voltage on outputs in 3-state mode. [4] the peak current is limited to 25 times the corresponding maximum current. [5] the maximum non-operating storage temperature is different t han the temperature for required shelf life which should be dete rmined based on required shelf lifetime. please refer to t he jedec spec (j-std-033b.1) for further details. [6] human body model: equivalent to dischar ging a 100 pf capacitor through a 1.5 k ? series resistor. table 5. limiting values in accordance with the absolute ma ximum rating system (iec 60134). [1] symbol parameter conditions min max unit v dd supply voltage (core and external rail) on pins v dd [2] ? 0.5 4.6 v v i input voltage 5 v tolerant i/o pins; only valid when the v dd supply voltage is present [3] ? 0.5 +5.5 v v x voltage on pin x no time limit; dc value on pins canh and canl ? 58 +58 v on pins stb, v cc , vdd_can ? 0.3 +7 v i dd supply current per supply pin [4] -100ma i ss ground current per ground pin [4] -100ma i latch i/o latch-up current ? (0.5v dd ) < v i < (1.5v dd ); t j < 125 ?c -100ma t stg storage temperature non-operating [5] ? 65 +150 ?c t j(max) maximum junction temperature -150 ?c p tot(pack) total power dissipation (per package) based on package heat transfer, not device power consumption -1.5w v esd electrostatic discharge voltage human body model; all pins except can on-chip transceiver pins canl, canh, stb, vdd_can, v cc , gnd on lpc11c22/c24 [6] ? 6500 +6500 v pins canh and canl on lpc11c22/c24 [6] ? 8000 +8000 v pins stb, vdd_can, v cc , gnd on lpc11c22/c24 [6] ? 4000 +4000 v
lpc11cx2_cx4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3.1 ? 15 may 2013 29 of 62 nxp semiconductors lpc11cx2/cx4 32-bit arm cortex-m0 microcontroller 9. static characteristics table 6. static characteristics t amb = ? 40 ? c to +85 ? c, unless otherwise specified. symbol parameter conditions min typ [1] max unit v dd supply voltage (core and external rail) on pins v dd 1.8 3.3 3.6 v i dd supply current active mode; code while(1){} executed from flash system clock = 12 mhz v dd = 3.3 v [2] [3] [4] [5] [6] [7] -3-m a system clock = 50 mhz v dd = 3.3 v [2] [3] [6] [5] [7] [8] -9-m a sleep mode; system clock = 12 mhz v dd = 3.3 v [2] [3] [4] [5] [6] [7] -2-m a deep-sleep mode; v dd = 3.3 v [2] [3] [5] [9] -6- ? a deep power-down mode; v dd = 3.3 v [2] [10] -2 2 0-n a standard port pins, reset i il low-level input current v i = 0 v; on-chip pull-up resistor disabled - 0.5 10 na i ih high-level input current v i =v dd ; on-chip pull-down resistor disabled - 0.5 10 na i oz off-state output current v o =0v; v o =v dd ; on-chip pull-up/down resistors disabled - 0.5 10 na v i input voltage pin configured to provide a digital function [11] [12] [13] 0- 5 . 0v v o output voltage output active 0 - v dd v v ih high-level input voltage 0.7v dd --v v il low-level input voltage - - 0.3v dd v v hys hysteresis voltage - 0.4 - v v oh high-level output voltage 2.0 v ? v dd ? 3.6 v; i oh = ? 4 ma v dd ? 0.4--v 1.8 v ? v dd < 2.0 v; i oh = ? 3 ma v dd ? 0.4--v v ol low-level output voltage 2.0 v ? v dd ? 3.6 v; i ol =4 ma --0 . 4v 1.8 v ? v dd < 2.0 v; i ol =3 ma --0.4v
lpc11cx2_cx4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3.1 ? 15 may 2013 30 of 62 nxp semiconductors lpc11cx2/cx4 32-bit arm cortex-m0 microcontroller i oh high-level output current v oh =v dd ? 0.4 v; 2.0 v ? v dd ? 3.6 v ? 4--m a 1.8 v ? v dd < 2.0 v ? 3--ma i ol low-level output current v ol =0.4v 2.0 v ? v dd ? 3.6 v 4--m a 1.8 v ? v dd < 2 . 0 v 3--m a i ohs high-level short-circuit output current v oh =0v [14] --? 45 ma i ols low-level short-circuit output current v ol =v dd [14] --5 0m a i pd pull-down current v i =5v 10 50 150 ? a i pu pull-up current v i =0v; 2.0 v ? v dd ? 3.6 v ? 15 ? 50 ? 85 ? a 1.8 v ? v dd < 2.0 v ? 10 ? 50 ? 85 ? a v dd lpc11cx2_cx4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3.1 ? 15 may 2013 31 of 62 nxp semiconductors lpc11cx2/cx4 32-bit arm cortex-m0 microcontroller [1] typical ratings are not guaranteed. the va lues listed are at room temperature (25 ? c), nominal supply voltages. [2] t amb =25 ? c. [3] i dd measurements were performed with all pins configured as gpio outputs driven low and pull-up resistors disabled. [4] irc enabled; system oscillator disabled; system pll disabled. [5] pin can_rxd pulled low externally. [6] bod disabled. [7] all peripherals disabled in the sysahbclkctrl register. peri pheral clocks to uart and spi0/1 disabled in system configuratio n block. [8] irc disabled; system oscill ator enabled; system pll enabled. [9] all oscillators and analog blocks turned off in the pdsleepcfg register; pdsleepcfg = 0x0000 18ff. [10] wakeup pin pulled high externally. [11] including voltage on outputs in 3-state mode. [12] v dd supply voltage must be present. i ol low-level output current v ol =0.4v 2.0 v ? v dd ? 3.6 v 4--m a 1.8 v ? v dd < 2 . 0 v 3--m a i ols low-level short-circuit output current v ol =v dd [14] --5 0m a i pd pull-down current v i =5v 10 50 150 ? a i pu pull-up current v i =0v 2.0 v ? v dd ? 3.6 v ? 15 ? 50 ? 85 ? a 1.8 v ? v dd < 2.0 v ? 10 ? 50 ? 85 ? a v dd lpc11cx2_cx4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3.1 ? 15 may 2013 32 of 62 nxp semiconductors lpc11cx2/cx4 32-bit arm cortex-m0 microcontroller [13] 3-state outputs go into 3-state mode in deep power-down mode. [14] allowed as long as the current limit does not exceed the maximum current allowed by the device. [15] to v ss . 9.1 adc characteristics [1] the adc is monotonic, there are no missing codes. [2] the differential linearity error (e d ) is the difference between the actual step width and the ideal step width. see figure 6 . [3] the integral non-linearity (e l(adj) ) is the peak difference between the center of the st eps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors. see figure 6 . [4] the offset error (e o ) is the absolute difference between the straight line which fits the actual cu rve and the straight line which fits the ideal curve. see figure 6 . [5] the gain error (e g ) is the relative difference in percent between the straight line fitting the actual transfe r curve after removing offset error, and the straight line which fits the ideal transfer curve. see figure 6 . [6] the absolute error (e t ) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated adc and the ideal transfer curve. see figure 6 . [7] t amb = 25 ? c; maximum sampling frequency f s = 400 ksamples/s and analog input capacitance c ia = 1 pf. [8] input resistance r i depends on the sampling frequency fs: r i = 1 / (f s ? c ia ). table 7. adc static characteristics t amb = ? 40 ? c to +85 ? c unless otherwise specified; adc frequency 4.5 mhz, v dd = 2.5 v to 3.6 v. symbol parameter conditions min typ max unit v ia analog input voltage 0 - v dd v c ia analog input capacitance - - 1 pf e d differential linearity error [1] [2] --? 1lsb e l(adj) integral non-linearity [3] --? 1.5 lsb e o offset error [4] --? 3.5 lsb e g gain error [5] --0 . 6% e t absolute error [6] --? 4lsb r vsi voltage source interface resistance --40k ? r i input resistance [7] [8] --2 . 5m ?
lpc11cx2_cx4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3.1 ? 15 may 2013 33 of 62 nxp semiconductors lpc11cx2/cx4 32-bit arm cortex-m0 microcontroller (1) example of an actual transfer curve. (2) the ideal transfer curve. (3) differential linearity error (e d ). (4) integral non-linearity (e l(adj) ). (5) center of a step of the actual transfer curve. fig 6. adc characteristics 002aaf426 1023 1022 1021 1020 1019 (2) (1) 1024 1018 1019 1020 1021 1022 1023 7 123456 7 6 5 4 3 2 1 0 1018 (5) (4) (3) 1 lsb (ideal) code out v dd ? v ss 1024 offset error e o gain error e g offset error e o v ia (lsb ideal ) 1 lsb =
lpc11cx2_cx4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3.1 ? 15 may 2013 34 of 62 nxp semiconductors lpc11cx2/cx4 32-bit arm cortex-m0 microcontroller 9.2 c_can on-chip, high-speed transceiver ch aracteristics table 8. static characteristics t amb = ? 40 ? c to +85 ? c; v cc = 4.5 v to 5.5 v; r l =60 ? ; unless otherwise specified; all voltages are defined with respect to ground; positive currents flow into the ic. also see figure 28 . symbol parameter conditions min typ max unit supply; pin vcc v cc supply voltage 4.5 - 5.5 v i cc supply current silent mode 0.1 1 2.5 ma normal mode recessive 2.5 5 10 ma dominant; can_txd = low 20 50 70 ma v uvd(vcc) undervoltage detection voltage on pin v cc 3.5 - 4.5 v i/o level adapter supply; pin vdd_can v dd supply voltage on pin vdd_can [1] 2.8 - 5.5 v i dd supply current on pin vdd_can; normal and silent modes recessive; can_txd = high 10 80 250 ? a dominant; can_txd = low 50 350 500 ? a v uvd(vdd_can) undervoltage detection voltage on pin vdd_can 1.3 - 2.7 v mode control input; pin stb v ih high-level input voltage 0.7v cc -v cc +0.3 v v il low-level input voltage ? 0.3 - 0.3v cc v i ih high-level input current 1 4 10 ? a i il low-level input current voltage on pin stb = 0 v ? 10+1 ? a bus lines; pins canh and canl v o(dom) dominant output voltage can_txd = low; t < t to(dom)txd pin canh 2.75 3.5 4.5 v pin canl 0.5 1.5 2.25 v v dom(tx)sym transmitter dominant voltage symmetry v dom(tx)sym = v cc ? v canh ? v canl ? 400 0 +400 mv v o(dif)bus bus differential output voltage can_txd = low; t < t to(dom)txd 1.5 - 3 v can_txd = high; recessive; no load ? 50 - +50 mv v o(rec) recessive output voltage normal and silent modes; can_txd = high; no load 20.5v cc 3v v th(rx)dif differential receiver threshold voltage normal and silent modes v cm(can) [2] = ? 12 v to +12 v 0.5 0.7 0.9 v v hys(rx)dif differential receiver hysteresis voltage normal and silent modes v cm(can) = ? 12 v to +12 v 50 120 400 mv i o(dom) dominant output current can_txd = low; t < t to(dom)txd ; v cc =5 v pin canh; v canh =0v ? 120 ? 70 ? 40 ma pin canl; v canl = 5 v/40 v 40 70 120 ma
lpc11cx2_cx4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3.1 ? 15 may 2013 35 of 62 nxp semiconductors lpc11cx2/cx4 32-bit arm cortex-m0 microcontroller [1] vdd_can must be equal to the vdd of the microcontroller [2] v cm(can) is the common mode voltage of canh and canl. i o(rec) recessive output current normal and silent modes; can_txd = high; v canh =v canl = ? 27 v to +32 v ? 5-+5 ma i l leakage current v cc =0v; v canh =v canl =5v ? 50+5 ? a r i input resistance 9 15 28 k ? ? r i input resistance deviation between v canh and v canl ? 30+3 % r i(dif) differential input resistance 19 30 52 k ? c i(cm) common-mode input capacitance --20pf c i(dif) differential input capacitance - - 10 pf temperature protection t j(sd) shutdown junction temperature -190- ?c table 8. static characteristics ?continued t amb = ? 40 ? c to +85 ? c; v cc = 4.5 v to 5.5 v; r l =60 ? ; unless otherwise specified; all voltages are defined with respect to ground; positive currents flow into the ic. also see figure 28 . symbol parameter conditions min typ max unit table 9. dynamic characteristics t amb = ? 40 ? c to +85 ?c; v cc = 4.5 v to 5.5 v; r l =60 ? unless specified otherwise. all voltages are defined with respect to ground. positive currents flow into the ic. symbol parameter conditions min typ max unit t to(dom)txd txd dominant time-out time can_txd = low; normal mode 0.3 1 12 ms
lpc11cx2_cx4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3.1 ? 15 may 2013 36 of 62 nxp semiconductors lpc11cx2/cx4 32-bit arm cortex-m0 microcontroller 9.3 bod static characteristics [1] interrupt levels are selected by writing the leve l value to the bod control register bodctrl, see lpc11cx user manual . 9.4 power consumption power measurements in active, sleep, and deep-sleep modes were performed under the following conditions (see lpc11cx user manual ): ? configure all pins as gpio with pull-up resistor disabled in the ioconfig block. ? configure gpio pins as outputs using the gpiondir registers. ? write 0 to all gpiondata registers to drive the outputs low. table 10. bod static characteristics [1] t amb =25 ? c. symbol parameter conditions min typ max unit v th threshold voltage interrupt level 1 assertion - 2.22 - v de-assertion - 2.35 - v interrupt level 2 assertion - 2.52 - v de-assertion - 2.66 - v interrupt level 3 assertion - 2.80 - v de-assertion - 2.90 - v reset level 0 assertion - 1.46 - v de-assertion - 1.63 - v reset level 1 assertion - 2.06 - v de-assertion - 2.15 - v reset level 2 assertion - 2.35 - v de-assertion - 2.43 - v reset level 3 assertion - 2.63 - v de-assertion - 2.71 - v
lpc11cx2_cx4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3.1 ? 15 may 2013 37 of 62 nxp semiconductors lpc11cx2/cx4 32-bit arm cortex-m0 microcontroller conditions: t amb = 25 ? c; active mode entered executing code while(1){} from flash; all peripherals disabled in the sysahbclkctrl regist er (sysahbclkctrl = 0x1f); all peripheral clocks disabled; internal pul l-up resistors disabled; bod di sabled; pin can_rxd pulled low externally. (1) system oscillator and syste m pll disabled; irc enabled. (2) system oscillator and system pll enabled; irc disabled. fig 7. active mode: typical supply current i dd versus supply voltage v dd for different system clock frequencies conditions: v dd = 3.3 v; active mode entered executing code while(1){} from flash; all peripherals disabled in the sysahbclkctrl regist er (sysahbclkctrl = 0x1f); all peripheral clocks disabled; internal pul l-up resistors disabled; bod di sabled; pin can_rxd pulled low externally. (1) system oscillator and syste m pll disabled; irc enabled. (2) system oscillator and system pll enabled; irc disabled. fig 8. active mode: typical supply current i dd versus temperature for different system clock frequencies v dd (v) 1.8 3.6 3.0 2.4 002aaf390 4 8 12 i dd (ma) 0 12 mhz (1) 24 mhz (2) 36 mhz (2) 48 mhz (2) temperature ( c) ?40 85 35 10 60 ?15 002aaf391 4 8 12 i dd (ma) 0 12 mhz (1) 24 mhz (2) 36 mhz (2) 48 mhz (2)
lpc11cx2_cx4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3.1 ? 15 may 2013 38 of 62 nxp semiconductors lpc11cx2/cx4 32-bit arm cortex-m0 microcontroller conditions: v dd = 3.3 v; sleep mode entered from fl ash; all peripheral s disabled in the sysahbclkctrl register (sysahbclk ctrl = 0x1f); all peripheral clocks disabled; internal pull-up resistors disabled; bod disabled; pin can_rx d pulled low externally. (1) system oscillator and syste m pll disabled; irc enabled. (2) system oscillator and system pll enabled; irc disabled. fig 9. sleep mode: typical supply current i dd versus temperature for different system clock frequencies conditions: bod disabled; all oscillators and analog blocks disabled in the pdsleepcfg register (pdsleepcfg = 0x0000 18ff); pin ca n_rxd pulled low externally. fig 10. deep-sleep mode: typical supply current i dd versus temperature for different supply voltages v dd 002aaf392 temperature ( c) ?40 85 35 10 60 ?15 2 6 4 8 i dd (ma) 0 12 mhz (1) 36 mhz (2) 48 mhz (2) 24 mhz (2) 002aaf394 temperature ( c) ?40 85 35 10 60 ?15 10 30 20 40 i dd (a) 0 3.6 v 3.3 v 2.0 v 1.8 v
lpc11cx2_cx4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3.1 ? 15 may 2013 39 of 62 nxp semiconductors lpc11cx2/cx4 32-bit arm cortex-m0 microcontroller fig 11. deep power-down mode: typical supply current i dd versus temperature for different supply voltages v dd 002aaf457 0.2 0.6 0.4 0.8 i dd (a) 0 temperature ( c) ?40 85 35 10 60 ?15 vdd = 3.6 v 3.3 v 2.0 v 1.8 v
lpc11cx2_cx4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3.1 ? 15 may 2013 40 of 62 nxp semiconductors lpc11cx2/cx4 32-bit arm cortex-m0 microcontroller 9.5 peripheral power consumption the supply current per peripheral is measured as the difference in supply current between the peripheral block enabled and the peripheral block disabled in the sysahbclkcfg and pdruncfg (for analog blocks) registers. all other blocks are disabled in both registers and no code is executed. me asured on a typical sample at t amb =25 ? c. unless noted otherwise, the system oscillator an d pll are running in both measurements. the supply currents are shown for system clock frequencies of 12 mhz and 48 mhz. table 11. power consumption for individual analog and digital blocks peripheral typical supply current in ma notes n/a 12 mhz 48 mhz irc 0.27 - - system oscillator running; pll off; independent of main clock frequency. system oscillator at 12 mhz 0.22 - - irc running; pll off; independent of main clock frequency. watchdog oscillator at 500 khz/2 0.004 - - system oscillator running; pll off; independent of main clock frequency. bod 0.051 - - independent of main clock frequency. main pll - 0.21 - adc - 0.08 0.29 clkout - 0.12 0.47 main clock divided by 4 in the clkoutdiv register. ct16b0 - 0.02 0.06 ct16b1 - 0.02 0.06 ct32b0 - 0.02 0.07 ct32b1 - 0.02 0.06 gpio - 0.23 0.88 gpio pins configured as outputs and set to low. direction and pin state are maintained if the gpio is disabled in the sysahbclkcfg register. ioconfig - 0.03 0.10 i2c - 0.04 0.13 rom - 0.04 0.15 spi0 - 0.12 0.45 spi1 - 0.12 0.45 uart - 0.22 0.82 c_can - 0.03 0.1 wdt - 0.02 0.06 main clock selected as clock source for the wdt.
lpc11cx2_cx4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3.1 ? 15 may 2013 41 of 62 nxp semiconductors lpc11cx2/cx4 32-bit arm cortex-m0 microcontroller 9.6 electrical pi n characteristics conditions: v dd = 3.3 v; on pin pio0_7. fig 12. high-drive output: typical high-level output voltage v oh versus high-level output current i oh . conditions: v dd = 3.3 v; on pins pio0_4 and pio0_5. fig 13. i 2 c-bus pins (high current sink): typical low-level output current i ol versus low-level output voltage v ol i oh (ma) 0 60 40 20 10 50 30 002aae990 2.8 2.4 3.2 3.6 v oh (v) 2 t = 85 c 25 c ?40 c v ol (v) 0 0.6 0.4 0.2 002aaf019 20 40 60 i ol (ma) 0 t = 85 c 25 c ?40 c
lpc11cx2_cx4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3.1 ? 15 may 2013 42 of 62 nxp semiconductors lpc11cx2/cx4 32-bit arm cortex-m0 microcontroller conditions: v dd = 3.3 v; standard port pins and pio0_7. fig 14. typical low-l evel output current i ol versus low-level output voltage v ol conditions: v dd = 3.3 v; standard port pins. fig 15. typical high-level output voltage v oh versus high-level output source current i oh v ol (v) 0 0.6 0.4 0.2 002aae991 5 10 15 i ol (ma) 0 t = 85 c 25 c ?40 c i oh (ma) 0 24 16 8 002aae992 2.8 2.4 3.2 3.6 v oh (v) 2 t = 85 c 25 c ?40 c
lpc11cx2_cx4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3.1 ? 15 may 2013 43 of 62 nxp semiconductors lpc11cx2/cx4 32-bit arm cortex-m0 microcontroller conditions: v dd = 3.3 v; standard port pins. fig 16. typical pull-up current i pu versus input voltage v i conditions: v dd = 3.3 v; standard port pins. fig 17. typical pull-down current i pd versus input voltage v i v i (v) 0 5 4 23 1 002aae988 ?30 ?50 ?10 10 i pu (a) ?70 t = 85 c 25 c ?40 c v i (v) 0 5 4 23 1 002aae989 40 20 60 80 i pd (a) 0 t = 85 c 25 c ?40 c
lpc11cx2_cx4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3.1 ? 15 may 2013 44 of 62 nxp semiconductors lpc11cx2/cx4 32-bit arm cortex-m0 microcontroller 10. dynamic characteristics 10.1 flash memory [1] number of program/erase cycles. [2] programming times are given for writing 256 bytes from ram to the flash. data must be written to the flash in blocks of 256 bytes. 10.2 external clock [1] parameters are valid over operating temp erature range unless otherwise specified. [2] typical ratings are not guaranteed. the va lues listed are at room temperature (25 ? c), nominal supply voltages. table 12. flash characteristics t amb = ? 40 ? c to +85 ? c, unless otherwise specified. symbol parameter conditions min typ max unit n endu endurance [1] 10000 100000 - cycles t ret retention time powered 10 - - years unpowered 20 - - years t er erase time sector or multiple consecutive sectors 95 100 105 ms t prog programming time [2] 0.95 1 1.05 ms table 13. dynamic characteristic: external clock t amb = ? 40 ? c to +85 ? c; v dd over specified ranges. [1] symbol parameter conditions min typ [2] max unit f osc oscillator frequency 1 - 25 mhz t cy(clk) clock cycle time 40 - 1000 ns t chcx clock high time t cy(clk) ? 0.4--ns t clcx clock low time t cy(clk) ? 0.4--ns t clch clock rise time - - 5 ns t chcl clock fall time - - 5 ns fig 18. external clock timing (with an amplitude of at least v i(rms) = 200 mv) t chcl t clcx t chcx t cy(clk) t clch 002aaa907
lpc11cx2_cx4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3.1 ? 15 may 2013 45 of 62 nxp semiconductors lpc11cx2/cx4 32-bit arm cortex-m0 microcontroller 10.3 internal oscillators [1] parameters are valid over operating temp erature range unless otherwise specified. [2] typical ratings are not guaranteed. the va lues listed are at room temperature (25 ? c), nominal supply voltages. [1] typical ratings are not guaranteed. the va lues listed are at room temperature (25 ? c), nominal supply voltages. [2] the typical frequency spread over processing and temperature (t amb = ?40 ? c to +85 ? c) is ? 40 %. [3] see the lpc11cx user manual . table 14. dynamic characteristic: internal oscillators t amb = ? 40 ? c to +85 ? c; 2.7 v ? v dd ? 3.6 v. [1] symbol parameter conditions min typ [2] max unit f osc(rc) internal rc oscillator frequency - 11.88 12 12.12 mhz conditions: frequency values are typical values. 12 mhz ?? 1 % accuracy is guaranteed for 2.7 v ? v dd ? 3.6 v and t amb = ?40 ? c to +85 ? c. variations between parts may cause the irc to fall outside the 12 mhz ? 1 % accuracy specification for voltages below 2.7 v. fig 19. internal rc oscillator frequency versus temperature table 15. dynamic characterist ics: watchdog oscillator symbol parameter conditions min typ [1] max unit f osc(int) internal oscillator frequency divsel = 0x1f, freqsel = 0x1 in the wdtoscctrl register; [2] [3] -7.8 - khz divsel = 0x00, freqsel = 0xf in the wdtoscctrl register [2] [3] - 1700 - khz 002aaf403 11.95 12.05 12.15 f (mhz) 11.85 temperature ( c) ?40 85 35 10 60 ?15 vdd = 3.6 v 3.3 v 3.0 v 2.7 v 2.4 v 2.0 v
lpc11cx2_cx4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3.1 ? 15 may 2013 46 of 62 nxp semiconductors lpc11cx2/cx4 32-bit arm cortex-m0 microcontroller 10.4 i/o pins [1] applies to standard port pins and reset pin. 10.5 i 2 c-bus [1] see the i 2 c-bus specification um10204 for details. [2] parameters are valid over operating temp erature range unless otherwise specified. [3] thd;dat is the data hold time that is measured from the falling edge of scl; applies to data in transmission and the acknowledge. [4] a device must internally provide a hold time of at least 300 ns for the sda signal (with respect to the v ih (min) of the scl signal) to bridge the undefined region of the falling edge of scl. [5] c b = total capacitance of one bus line in pf. table 16. dynamic characteristic: i/o pins [1] t amb = ? 40 ? c to +85 ? c; 3.0 v ? v dd ? 3.6 v. symbol parameter conditions min typ max unit t r rise time pin configured as output 3.0 - 5.0 ns t f fall time pin configured as output 2.5 - 5.0 ns table 17. dynamic characteristic: i 2 c-bus pins [1] t amb = ? 40 ? c to +85 ? c. [2] symbol parameter conditions min max unit f scl scl clock frequency standard-mode 0 100 khz fast-mode 0 400 khz fast-mode plus 0 1 mhz t f fall time [4] [5] [6] [7] of both sda and scl signals standard-mode - 300 ns fast-mode 20 + 0.1 ? c b 300 ns fast-mode plus - 120 ns t low low period of the scl clock standard-mode 4.7 - ? s fast-mode 1.3 - ? s fast-mode plus 0.5 - ? s t high high period of the scl clock standard-mode 4.0 - ? s fast-mode 0.6 - ? s fast-mode plus 0.26 - ? s t hd;dat data hold time [3] [4] [8] standard-mode 0 - ? s fast-mode 0 - ? s fast-mode plus 0 - ? s t su;dat data set-up time [9] [10] standard-mode 250 - ns fast-mode 100 - ns fast-mode plus 50 - ns
lpc11cx2_cx4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3.1 ? 15 may 2013 47 of 62 nxp semiconductors lpc11cx2/cx4 32-bit arm cortex-m0 microcontroller [6] the maximum t f for the sda and scl bus lines is specified at 300 ns. the maximum fall time for the sda output stage t f is specified at 250 ns. this allows series protection resistors to be connected in between the sda and the scl pins and the sda/scl bus lines without exceeding the maximum specified t f . [7] in fast-mode plus, fall time is specified the same for both output stage and bus timing. if series resistors are used, designers should allow for this when considering bus timing. [8] the maximum t hd;dat could be 3.45 ? s and 0.9 ? s for standard-mode and fast-mode but must be less than the maximum of t vd;dat or t vd;ack by a transition time (see um10204 ). this maximum must only be met if the device does not stretch the low period (t low ) of the scl signal. if the clock stretches the scl, the data must be valid by the set-up time before it releases the clock. [9] tsu;dat is the data set-up time that is measured wi th respect to the rising edge of scl; applies to data in transmission and the acknowledge. [10] a fast-mode i 2 c-bus device can be used in a standard-mode i 2 c-bus system but the requirement t su;dat = 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the lo w period of the scl signal, it must output the next data bit to the sda line t r(max) + t su;dat = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c-bus specification) before the scl line is released. also the acknowledge timing must meet this set-up time. 10.6 spi interfaces fig 20. i 2 c-bus pins clock timing 002aaf425 t f 70 % 30 % sda t f 70 % 30 % s 70 % 30 % 70 % 30 % t hd;dat scl 1 / f scl 70 % 30 % 70 % 30 % t vd;dat t high t low t su;dat table 18. dynamic characteristics of spi pins in spi mode symbol parameter conditions min typ max unit spi master (in spi mode) t cy(clk) clock cycle time full-duplex mode [1] 50 - - ns when only transmitting [1] 40 ns t ds data set-up time in spi mode 2.4 v ? v dd ? 3.6 v [2] 15 - - ns 2.0 v ? v dd < 2.4 v [2] 20 ns 1.8 v ? v dd < 2.0 v [2] 24 - - ns t dh data hold time in spi mode [2] 0-- n s t v(q) data output valid time in spi mode [2] -- 1 0 n s t h(q) data output hold time in spi mode [2] 0-- n s spi slave (in spi mode) t cy(pclk) pclk cycle time 20 - - ns
lpc11cx2_cx4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3.1 ? 15 may 2013 48 of 62 nxp semiconductors lpc11cx2/cx4 32-bit arm cortex-m0 microcontroller [1] t cy(clk) = (sspclkdiv ? (1 + scr) ? cpsdvsr) / f main . the clock cycle time deriv ed from the spi bit rate t cy(clk) is a function of the main clock frequency f main , the spi peripheral clock divider (sspclkdiv), the spi scr parameter (specified in the ssp0cr0 register), and the spi cpsdvsr parameter (specified in the spi clock prescale register). [2] t amb = ?40 ? c to 85 ? c. [3] t cy(clk) = 12 ? t cy(pclk) . [4] t amb = 25 ? c; for normal voltage supply range: v dd = 3.3 v. t ds data set-up time in spi mode [3] [4] 0-- n s t dh data hold time in spi mode [3] [4] 3 ? t cy(pclk) + 4 - - ns t v(q) data output valid time in spi mode [3] [4] -- 3 ? t cy(pclk) + 11 ns t h(q) data output hold time in spi mode [3] [4] -- 2 ? t cy(pclk) + 5 ns table 18. dynamic characteristics of spi pins in spi mode symbol parameter conditions min typ max unit pin names sck, miso, and mosi refer to pins for both spi peripherals, spi0 and spi1. fig 21. spi master timing in spi mode sck (cpol = 0) mosi miso t cy(clk) t clk(h) t clk(l) t ds t dh t v(q) data valid data valid t h(q) sck (cpol = 1) data valid data valid mosi miso t ds t dh data valid data valid t h(q) data valid data valid t v(q) cpha = 1 cpha = 0 002aae829
lpc11cx2_cx4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3.1 ? 15 may 2013 49 of 62 nxp semiconductors lpc11cx2/cx4 32-bit arm cortex-m0 microcontroller pin names sck, miso, and mosi refer to pins for both spi peripherals, spi0 and spi1. fig 22. spi slave timing in spi mode sck (cpol = 0) mosi miso t cy(clk) t clk(h) t clk(l) t ds t dh t v(q) data valid data valid t h(q) sck (cpol = 1) data valid data valid mosi miso t ds t dh t v(q) data valid data valid t h(q) data valid data valid cpha = 1 cpha = 0 002aae830
lpc11cx2_cx4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3.1 ? 15 may 2013 50 of 62 nxp semiconductors lpc11cx2/cx4 32-bit arm cortex-m0 microcontroller 11. application information 11.1 adc usage notes the following guidelines show how to increase the performance of the adc in a noisy environment beyond the adc specifications listed in ta b l e 7 : ? the adc input trace must be short and as close as possible to the lpc11cx2/cx4 chip. ? the adc input traces must be shielded from fast switching digital signals and noisy power supply lines. ? because the adc and the digital core share the same power supply, the power supply line must be adequately filtered. ? to improve the adc performance in a very no isy environment, put the device in sleep mode during the adc conversion. 11.2 xtal input the input voltage to the on-chip oscillators is limited to 1.8 v. if the oscillator is driven by a clock in slave mode, it is recommended that th e input be coupled through a capacitor with c i = 100 pf. to limit the input voltage to the specified range, choose an additional capacitor to ground c g which attenuates the input voltage by a factor c i /(c i + c g ). in slave mode, a minimum of 200 mv (rms) is needed. in slave mode the input clock signal should be coupled by means of a capacitor of 100 pf ( figure 23 ), with an amplitude between 200 mv (rms) and 1000 mv (rms). this corresponds to a square wave signal with a signal swing of between 280 mv and 1.4 v. the xtalout pin in this configur ation can be left unconnected. external components and models used in oscillation mode are shown in figure 24 and in ta b l e 1 9 and ta b l e 2 0 . since the feedback resistance is integrated on chip, only a crystal and the capacitances c x1 and c x2 need to be connected externally in case of fundamental mode oscillation (the fundamental frequenc y is represen ted by l, c l and r s ). capacitance c p in figure 24 represents the parallel package capacitance and should not be larger than 7 pf. parameters f osc , c l , r s and c p are supplied by the crystal manufacturer (see ta b l e 1 9 ). fig 23. slave mode operation of the on-chip oscillator lpc1xxx xtalin c i 100 pf c g 002aae788
lpc11cx2_cx4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3.1 ? 15 may 2013 51 of 62 nxp semiconductors lpc11cx2/cx4 32-bit arm cortex-m0 microcontroller 11.3 xtal printed circuit bo ard (pcb) layout guidelines the crystal should be connected on the pcb as close as poss ible to the oscillator input and output pins of the chip. take care that the load capacitors c x1 , c x2 , and c x3 in case of third overtone crystal usage have a common ground plane. the external components must also be connected to the ground plain. loops must be made as small as possible in fig 24. oscillator modes and models: oscillation mode of operation and external crystal model used for c x1 /c x2 evaluation table 19. recommended values for c x1 /c x2 in oscillation mode (crystal and external components parameters) low frequency mode fundamental oscillation frequency f osc crystal load capacitance c l maximum crystal series resistance r s external load capacitors c x1 , c x2 1 mhz - 5 mhz 10 pf < 300 ? 18 pf, 18 pf 20 pf < 300 ? 39 pf, 39 pf 30 pf < 300 ? 57 pf, 57 pf 5 mhz - 10 mhz 10 pf < 300 ? 18 pf, 18 pf 20 pf < 200 ? 39 pf, 39 pf 30 pf < 100 ? 57 pf, 57 pf 10 mhz - 15 mhz 10 pf < 160 ? 18 pf, 18 pf 20 pf < 60 ? 39 pf, 39 pf 15 mhz - 20 mhz 10 pf < 80 ? 18 pf, 18 pf table 20. recommended values for c x1 /c x2 in oscillation mode (crystal and external components parameters) high frequency mode fundamental oscillation frequency f osc crystal load capacitance c l maximum crystal series resistance r s external load capacitors c x1 , c x2 15 mhz - 20 mhz 10 pf < 180 ? 18 pf, 18 pf 20 pf < 100 ? 39 pf, 39 pf 20 mhz - 25 mhz 10 pf < 160 ? 18 pf, 18 pf 20 pf < 80 ? 39 pf, 39 pf 002aaf424 lpc1xxx xtalin xtalout c x2 c x1 xtal = c l c p r s l
lpc11cx2_cx4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3.1 ? 15 may 2013 52 of 62 nxp semiconductors lpc11cx2/cx4 32-bit arm cortex-m0 microcontroller order to keep the noise coupled in via the pcb as small as possible. also parasitics should stay as small as possible. values of c x1 and c x2 should be chosen smaller accordingly to the increase in parasitics of the pcb layout. 11.4 standard i/o pad configuration figure 25 shows the possible pin modes for standard i/o pins with analog input function: ? digital output driver ? digital input: pull-up enabled/disabled ? digital input: pull-down enabled/disabled ? digital input: repeater mode enabled/disabled ? analog input fig 25. standard i/o pad configuration pin v dd esd v ss esd v dd weak pull-up weak pull-down output enable repeater mode enable output pull-up enable pull-down enable data input analog input select analog input 002aaf304 pin configured as digital output driver pin configured as digital input pin configured as analog input
lpc11cx2_cx4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3.1 ? 15 may 2013 53 of 62 nxp semiconductors lpc11cx2/cx4 32-bit arm cortex-m0 microcontroller 11.5 reset pad configuration 11.6 c_can with external tr ansceiver (lpc11c12/c14 only) fig 26. reset pad configuration v ss reset 002aaf274 v dd v dd v dd r pu esd esd 20 ns rc glitch filter pin fig 27. connecting the c_can to an external transceiver (lpc11c12/c14) s txd rxd lpc11c12/c14 piox_y can_txd can_rxd gnd v cc canh canh canl canl 5 v bat 3 v v io 002aaf911 tjf1051
lpc11cx2_cx4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3.1 ? 15 may 2013 54 of 62 nxp semiconductors lpc11cx2/cx4 32-bit arm cortex-m0 microcontroller 11.7 c_can with on-chip, high-speed transceiver (lpc11c22/c24 only) fig 28. connecting the can hi gh-speed transceiver to the can bus (lpc11c22/c24) v dd gnd v cc canh canh canl canl 5 v v dd 3 v vdd_can 002aaf910 lpc11c22/c24 can high-speed transceiver c_can can_txd can_rxd std
lpc11cx2_cx4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3.1 ? 15 may 2013 55 of 62 nxp semiconductors lpc11cx2/cx4 32-bit arm cortex-m0 microcontroller 12. package outline fig 29. package outline sot313-2 (lqfp48) unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z ywv references outline version european projection issue date iec jedec jeita mm 1.6 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 7.1 6.9 0.5 9.15 8.85 0.95 0.55 7 0 o o 0.12 0.1 0.2 1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot313-2 ms-026 136e05 00-01-19 03-02-25 d (1) (1)(1) 7.1 6.9 h d 9.15 8.85 e z 0.95 0.55 d b p e e b 12 d h b p e h v m b d z d a z e e v m a 1 48 37 36 25 24 13 a 1 a l p detail x l (a ) 3 a 2 x y c w m w m 0 2.5 5 mm scale pin 1 index lqfp48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm sot313-2
lpc11cx2_cx4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3.1 ? 15 may 2013 56 of 62 nxp semiconductors lpc11cx2/cx4 32-bit arm cortex-m0 microcontroller 13. soldering fig 30. reflow soldering of the lqfp48 package sot313-2 dimensions in mm occupied area footprint information for reflow soldering of lqfp48 package ax bx gx gy hy hx ayby p1 d2 (8) d1 (0.125) ax ay bx by d1 d2 gx gy hx hy 10.350 p2 0.560 10.350 7.350 7.350 p1 0.500 0.280 c 1.500 0.500 7.500 7.500 10.650 10.650 sot313-2_fr solder land c generic footprint pattern refer to the package outline drawing for actual layout p2
lpc11cx2_cx4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3.1 ? 15 may 2013 57 of 62 nxp semiconductors lpc11cx2/cx4 32-bit arm cortex-m0 microcontroller 14. abbreviations table 21. abbreviations acronym description adc analog-to-digital converter ahb advanced high-performance bus apb advanced peripheral bus api application programming interface bod brownout detection can controller area network gpio general purpose input/output pll phase-locked loop rc resistor-capacitor sdo service data object spi serial peripheral interface ssi serial synchronous interface ssp synchronous serial port uart universal asynchronous receiver/transmitter
lpc11cx2_cx4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3.1 ? 15 may 2013 58 of 62 nxp semiconductors lpc11cx2/cx4 32-bit arm cortex-m0 microcontroller 15. revision history table 22. revision history document id release date data sheet status change notice supersedes lpc11cx2_cx4 v.3.1 20130515 product data sheet - lpc11cx2_cx4 v.3 modifications: ? table 3 and table 4 : added ?5 v tolerant pad? to reset /pio0_0 table note. ? table 5 : ? added table note 2 . ? corrected v dd min and max. ? table 8 : added ta b l e n o t e 1 . ? table 10 : removed bod interrupt level 0. lpc11cx2_cx4 v.3 20110627 product data sheet - lpc11c12_c14 v.2 modifications: ? i 2 c-bus pins configured as standard mode pins, parameter i ol changed to 3.5 ma (minimum) for 2.0 v ? v dd ? 3.6 v. ? parameter v x added to table 5 ?limiting values?. ? c_can power consumption data added to table 11. ? adc sampling frequency corrected in table 7 (table note 7). ? reflow soldering footprint drawing added (section 13). ? pull-up level specified in table 3 and table 4. ? parameter t cy(clk) corrected on table 18. ? condition for parameter t stg in table 5 updated. ? table note 5 of table 5 updated. ? table 18 t~cy(clk) condition changed from ?wh en only receiving? to ?full-duplex mode? lpc11cx2_cx4 v.2 20101203 product data sheet - lpc11c12_c14 v.1 modifications: ? parts lpc11c22 and lpc11c24 added. ? pin description for parts lpc11c22 and lpc11c24 added (table 4). ? static characteristics for can transceiver added (table 8). ? description of high-speed, on-chip can transceiver added (lpc11c22/c24). see section 7.11.2. ? application diagram for connecting the c_can to an external transceiver added (section 11.6). ? application diagram for high-speed, on-chip can transceiver added (section 11.7). ? typical value for parameter n endu added in table 12 ?flash characteristics?. ? description of reset and wakekup pins up dated in table 3. ? pll output frequency limited to < 100 mhz in section 7.16.2 ?system pll?. ? parameter v hys for i 2 c bus pins: typical value corrected v hys = 0.05v dd in table 6. lpc11c12_c14 v.1 20100921 product data sheet - -
lpc11cx2_cx4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3.1 ? 15 may 2013 59 of 62 nxp semiconductors lpc11cx2/cx4 32-bit arm cortex-m0 microcontroller 16. legal information 16.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. 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nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification.
lpc11cx2_cx4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3.1 ? 15 may 2013 60 of 62 nxp semiconductors lpc11cx2/cx4 32-bit arm cortex-m0 microcontroller export control ? this document as well as the item(s) described herein may be subject to export control regu lations. export might require a prior authorization from competent authorities. non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive app lications beyond nxp semiconductors? standard warranty and nxp semiconduct ors? product specifications. 16.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. i 2 c-bus ? logo is a trademark of nxp b.v. 17. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
lpc11cx2_cx4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 3.1 ? 15 may 2013 61 of 62 continued >> nxp semiconductors lpc11cx2/cx4 32-bit arm cortex-m0 microcontroller 18. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 ordering information . . . . . . . . . . . . . . . . . . . . . 3 4.1 ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 5 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7 7 functional description . . . . . . . . . . . . . . . . . . 15 7.1 arm cortex-m0 processor . . . . . . . . . . . . . . . 15 7.2 on-chip flash program memo ry . . . . . . . . . . . 15 7.3 on-chip sram . . . . . . . . . . . . . . . . . . . . . . . . 15 7.4 memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.5 nested vectored interrupt controller (nvic) . 16 7.5.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.5.2 interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 17 7.6 ioconfig block . . . . . . . . . . . . . . . . . . . . . . 17 7.7 fast general purpose parallel i/o . . . . . . . . . . 17 7.7.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.8 uart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.8.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.9 spi serial i/o controller. . . . . . . . . . . . . . . . . . 18 7.9.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.10 i 2 c-bus serial i/o controller . . . . . . . . . . . . . . 18 7.10.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.11 c_can controller . . . . . . . . . . . . . . . . . . . . . . 19 7.11.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.11.2 on-chip, high-speed can transceiver . . . . . . 20 7.11.2.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.11.2.2 normal mode . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.11.2.3 silent mode. . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.11.2.4 undervoltage protection . . . . . . . . . . . . . . . . . 20 7.11.2.5 thermal protection . . . . . . . . . . . . . . . . . . . . . 20 7.11.2.6 time-out function . . . . . . . . . . . . . . . . . . . . . . 21 7.12 10-bit adc . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.12.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.13 general purpose external event counter/timers . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.13.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.14 system tick timer . . . . . . . . . . . . . . . . . . . . . . 22 7.15 watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . 22 7.15.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.16 clocking and power control . . . . . . . . . . . . . . 22 7.16.1 crystal oscillators . . . . . . . . . . . . . . . . . . . . . . 22 7.16.1.1 internal rc oscillator . . . . . . . . . . . . . . . . . . . 23 7.16.1.2 system oscillator . . . . . . . . . . . . . . . . . . . . . . 23 7.16.1.3 watchdog oscillator . . . . . . . . . . . . . . . . . . . . 24 7.16.2 system pll . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.16.3 clock output . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.16.4 wake-up process . . . . . . . . . . . . . . . . . . . . . . 24 7.16.5 power control . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.16.5.1 sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.16.5.2 deep-sleep mode. . . . . . . . . . . . . . . . . . . . . . 25 7.16.5.3 deep power-down mode . . . . . . . . . . . . . . . . 25 7.17 system control . . . . . . . . . . . . . . . . . . . . . . . . 25 7.17.1 start logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.17.2 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.17.3 brownout detection . . . . . . . . . . . . . . . . . . . . 25 7.17.4 code security (code read protection - crp) 26 7.17.5 bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.17.6 apb interface . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.17.7 ahblite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.17.8 external interr upt inputs . . . . . . . . . . . . . . . . . 27 7.18 emulation and debugging . . . . . . . . . . . . . . . 27 8 limiting values . . . . . . . . . . . . . . . . . . . . . . . . 28 9 static characteristics . . . . . . . . . . . . . . . . . . . 29 9.1 adc characteristics . . . . . . . . . . . . . . . . . . . . 32 9.2 c_can on-chip, high-speed transceiver characteristics . . . . . . . . . . . . . . . . . . . . . . . . 34 9.3 bod static characteristics . . . . . . . . . . . . . . . 36 9.4 power consumption . . . . . . . . . . . . . . . . . . . 36 9.5 peripheral power consumption . . . . . . . . . . . 40 9.6 electrical pin characteristics. . . . . . . . . . . . . . 41 10 dynamic characteristics. . . . . . . . . . . . . . . . . 44 10.1 flash memory . . . . . . . . . . . . . . . . . . . . . . . . 44 10.2 external clock. . . . . . . . . . . . . . . . . . . . . . . . . 44 10.3 internal oscillators . . . . . . . . . . . . . . . . . . . . . 45 10.4 i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 10.5 i 2 c-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 10.6 spi interfaces. . . . . . . . . . . . . . . . . . . . . . . . . 47 11 application information . . . . . . . . . . . . . . . . . 50 11.1 adc usage notes. . . . . . . . . . . . . . . . . . . . . . 50 11.2 xtal input . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 11.3 xtal printed circuit board (pcb) layout guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 11.4 standard i/o pad configuration . . . . . . . . . . . 52 11.5 reset pad configuration . . . . . . . . . . . . . . . . . 53 11.6 c_can with external transceiver (lpc11c12/c14 only) . . . . . . . . . . . . . . . . . . 53 11.7 c_can with on-chip, high-speed transceiver (lpc11c22/c24 only) . . . . . . . . . . . . . . . . . . 54 12 package outline. . . . . . . . . . . . . . . . . . . . . . . . 55 13 soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
nxp semiconductors lpc11cx2/cx4 32-bit arm cortex-m0 microcontroller ? nxp b.v. 2013. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 15 may 2013 document identifier: lpc11cx2_cx4 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 14 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 57 15 revision history . . . . . . . . . . . . . . . . . . . . . . . . 58 16 legal information. . . . . . . . . . . . . . . . . . . . . . . 59 16.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 59 16.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 16.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 16.4 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 60 17 contact information. . . . . . . . . . . . . . . . . . . . . 60 18 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

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